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    Verlog Intro

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    Verilog is a hardware description language used to model and simulate digital circuits. It allows modeling at different levels of abstraction such as behavioral, dataflow, and structural. Some key uses of Verilog include logic simulation to verify circuit operation and synthesis to transform descriptions into logic gates. Verilog supports concepts like modules to describe circuit components and uses syntax similar to C for coding circuit behaviors and structures.

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    Verlog Intro

    Uploaded by

    Guru
    41 views16 pages
    Verilog is a hardware description language used to model and simulate digital circuits. It allows modeling at different levels of abstraction such as behavioral, dataflow, and structural. Some key uses of Verilog include logic simulation to verify circuit operation and synthesis to transform descriptions into logic gates. Verilog supports concepts like modules to describe circuit components and uses syntax similar to C for coding circuit behaviors and structures.

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    Verilog is a hardware description language used to model and simulate digital circuits. It allows modeling at different levels of abstraction such as behavioral, dataflow, and structural. Some key uses of Verilog include logic simulation to verify circuit operation and synthesis to transform descriptions into logic gates. Verilog supports concepts like modules to describe circuit components and uses syntax similar to C for coding circuit behaviors and structures.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    41 views16 pages

    Verlog Intro

    Uploaded by

    Guru
    Verilog is a hardware description language used to model and simulate digital circuits. It allows modeling at different levels of abstraction such as behavioral, dataflow, and structural. Some key uses of Verilog include logic simulation to verify circuit operation and synthesis to transform descriptions into logic gates. Verilog supports concepts like modules to describe circuit components and uses syntax similar to C for coding circuit behaviors and structures.

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    © All Rights Reserved
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    of 16

    VERILOG HDL

    Hardware Description Languages


    • High Level Language
    –To describe the circuits by syntax and
    sentences
    –As oppose to circuit described by schematics
    •Widely used HDLs
    –Verilog – Similar to C
    –VHDL – Similar to PASCAL
    Simulation and Synthesis
    • The two major purposes of HDLs are logic
    simulation and synthesis
    • During simulation, inputs are applied to a
    module, and the outputs are checked to verify
    that the module operates correctly
    • During synthesis, the textual description of a
    module is transformed into logic gates
    • Circuit descriptions in HDL resemble code in a
    programming language. But the code is
    intended to represent hardware
    Level of Abstraction

    Performance specifications
    Behaviour Test benches
    Sequential descriptions
    State machines
    Dataflow Register transfers Level of
    Selected assignments abstraction
    Arithmetic operations
    Boolean equations
    Structure Hierarchy
    Physical information
    Verilog HDL
    • Verilog was developed by Gateway Design
    Automation as a proprietary language for logic
    simulation in 1984.
    •Gateway was acquired by Cadence in 1989
    •Verilog was made an open standard in 1990
    under the control of Open Verilog International.
    •The language became an IEEE standard in 1995
    (IEEE STD 1364) and was updated in 2001 and
    2005.
    Verilog HDL
    • What is Verilog HDL?

    Verilog HDL is a Hardware Description


    Language that can be used to model a digital
    system at many levels of abstraction:
    – Behavioral level
    – Data Flow level
    – Structural level(gate Level)
    – Switch-level
    MODULE
    Basic building block in Verilog
    Components of Verilog Module
    Full Adder
    Full adder Gate level or structural modeling
    Full Adder Dataflow Modelling
    module full_adder( S= A + B + C
        input a,
        input b, cout = (A + B).C + AB
        input cin, (or)
        output s,
    cout = AB + BC + AC
        output cout,
        );
    assign x = a ^ b ;
    assign y = x & cin ;
    assign z = a & b ;
    assign s = x ^ cin ;
    assign cout = y | z ;
    endmodule
    Full Adder Behavioural Modelling
    module full_adder( A, B, Cin, S, Cout);
    input wire A, B, Cin;
    output reg S, Cout;
    always @(A or B or Cin)
    begin
    if(A==0 && B==0 && Cin==0) begin S=0; Cout=0; end
    else if(A==0 && B==0 && Cin==1) begin S=1; Cout=0; end
    else if(A==0 && B==1 && Cin==0) begin S=1; Cout=0; end
    else if(A==0 && B==1 && Cin==1) begin S=0; Cout=1; end
    else if(A==1 && B==0 && Cin==0) begin S=1; Cout=0; end
    else if(A==1 && B==0 && Cin==1) begin S=0; Cout=1; end
    else if(A==1 && B==1 && Cin==0) begin S=0; Cout=1; end
    else if(A==1 && B==1 && Cin==1) begin S=1; Cout=1; end
    end
    endmodule
    Full Adder Behavioural Modelling
    full_adder( A, B, Cin, S, Cout);
    input wire A, B, Cin;
    output reg S, Cout;
    always @(A or B or Cin)
    begin
    S = A ^ B ^ Cin;
    Cout = A&B | (A^B) & Cin;
    end
    endmodule
    Full Adder Behavioural Modelling
    full_adder(input wire A, B, Cin, output reg S, output reg Cout);
    always @(A or B or Cin)
    begin
    case (A | B | Cin)
    3'b000: begin S = 0; Cout = 0; end
    3'b001: begin S = 1; Cout = 0; end
    3'b010: begin S = 1; Cout = 0; end
    3'b011: begin S = 0; Cout = 1; end
    3'b100: begin S = 1; Cout = 0; end
    3'b101: begin S = 0; Cout = 1; end
    3'b110: begin S = 0; Cout = 1; end
    3'b111: begin S = 1; Cout = 1; end
    endcase
    End
    endmodule

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