PRIYANKA KUMARI (Low Power SRAM)

TPT PRESENTATION
ON
LOW POWER STATIC RANDOM ACCESS MEMORY
Presented by:- Under the Supervision of:-
Priyanka Kumari Pushpendra Dwivedi

Roll. No:-21MECE06 Asst. Professor
Reg. No:-21141108017 BCE Bhagalpur
Department of Electronics and Communication Engineering

Bhagalpur College of Engineering, Bhagalpur
CONTENTS
 Introduction
 Purpose
 Research problem statement
 Objective
 Research methodology
 Work done
 Application
 Advantage
 Disadvantage
 Expected outcome
 Future plan
 References
INTRODUCTION
 Static RAMs use a memory cell with internal feedback that retains its value
as long as power is applied. It has the following attractive properties.
 Denser than flip-flops
 Compatible with standard CMOS processes
 Faster than DRAM
 Easier to use than DRAM.

PURPOSE
 Develop a functioning SRAM memory device.
 Implement design features to reduce overall power consumption.
 Design a robust memory device that operates over.
 A large range of temperatures, voltages, and process corners.

RESARCH PROBLEM STATEMENT
 The main issue in VLSI design are optimizing speed, scaling in silicon
technology and increased packing density.
 These issues account for increased power dissipation in SoC (System on

Chips) making them unsuitable for portable operations.
 Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a
low power SRAM design to maximize the run time with minimum
requirements on size, battery life and weight allocated to batteries.
OBJECTIVE
 To design low power SRAM memory cells of different configurations like

6T, 8T and 9T (whereT represents the transistor).
 compare their performance parameters like-- Read and write delay.
 Leakage power consumption.
 Static noise margins (during hold, read and write).

RESEARCH METHODOLOGY
 The working of basic cell we have to assume
the previous state of cell. Basically by this
circuit we can do only read operation.
 the input voltage we can store the value

SRAM cell.
 First we applied the input voltage to the

inverter one. Then we got the output of
inverter one that is input of the second
inverter.
 After the pass transistor gets turn on by the

words election .The value is passing through
the access transistor to the bit line and bit line
bar. From the bit line and bit line bar, finally
Fig. Schematic of basic 6T CMOS SRAM Cell
we got output. In this way the read operation
gets performed
WORK DONE
FIG:-READ WAVEFORM OF 6T SRAM FIG:-WRITE WAVEFORM FIG:-STATIC NOISE MARGINS

Fig:- Read SNM of 6T SRAM cell Fig:- Write SNM of 6T SRAM cell
APPLICATION
 Body area networks (bans) require the design of power-efficient SRAM.
 Two cross coupled cmos inverters.
 Factory automation (fa).
 Industrial equipment, and
 The smart grids.

ADVANTAGE
 Static power dissipation is very small.
 including high noise immunity due to large noise margins.
 Ability to operate at lower power supply voltage.
 Static power dissipation is small and it is limited by the leakage current.
 High noise margin.

DISADVANTAGE
 Large cell size.
 complexity of the CMOS processes.
 Tendency to exhibit 'latch-up' phenomena.

EXPECTED OUTCOME
 The compared parameters were read delay, write delay, leakage power consumption and static
noise margin(during hold, read and write).
 Increasing the numbers of transistors read and write delays and leakage power consumption
is increased as the cell area increases.
 This shows that the 6t SRAM cell is better but based on noise margin it shows poor data
stability.
 The low power and better stability as the structure is such modified that it uses the single bit
line for charging and discharging and providing dual port operation also. To increase their
reliability of SRAM cell, the lifetime of battery is a prime concerned at the cost of speed.
 Reduction in the power consumption reduces the problems associated with high temperature
and also provides an additional benefit in terms of the extended life of the battery.
FUTURE PLAN
 To perform the write operation in the SRAM cell to flip the data value, nearly full voltage
swings is required on the bit line.
 voltage swing reduction is an effective way to decrease the power dissipation. the future
course of action involves effective reduction of leakage in an SRAM cell.
 It is proposed here that appropriate leakage reduction techniques would be developed with an
emphasis on the reduction of gate leakage. Leakage reduction in SRAM is also possible using
self controllable switch either at the upper end of the cell to reduce supply voltage (USR
scheme) or at the lower end of the cell to raise the potential of the ground node (LPR
scheme). This method would also be tested for its efficacy when this work is advanced.

REFERENCES
Hong Zhu and Volkan Kursun , “A Comprehensive Comparison of Data Stability Enhancement
Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations” IEEE Transactions
On Circuits And Systems—I: Regular Papers, Vol. 61, No. 5, May 2014.
Wasim Hussain and Shah M.Jahinuzzaman, “A read-decoupled gated-ground SRAM architecture for low-
Power embedded memories” INTEGRATION, the VLSI journal 45(2012) 229–236.
Evert Seevinck, Frans J. List And Jan Lohstroh, “Static-Noise Margin Analysis of MOSSRAM Cells”
IEEE JOURNAL OF SOLID-STATE CIRCUITS , VOL. SC-22, NO. 5, Oct-1987.
Ankit Mitra, “Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High
Speed Applications", World Academy of Science, Engineering and Technology International Journal of
Electrical, Computer, Electronics and Communication Engineering Vol:8 No:4, 2014.
Baker Mohammad, “Low Leakage Power SRAM Cell for Embedded Memory” International Conference
on Innovations in Information Technology, 2011.
Sung-Mo Kang Yusuf Leblebici Chulwoo Kim " CMOS Digital integrated circuit" INDIAN EDITION 4TH
EDITION "SRAM, Full CMOS SRAM Cell, Application ,advantage ,disadvantage " vol no 10 (page no-
448,450,481,482,483).

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TPT PRESENTATION

Presented by:- Under the Supervision of:-

Priyanka Kumari Pushpendra Dwivedi

Department of Electronics and Communication Engineering

 Denser than flip-flops

 Compatible with standard CMOS processes

 Faster than DRAM

 Easier to use than DRAM.

 Develop a functioning SRAM memory device.

 Implement design features to reduce overall power consumption.

 Design a robust memory device that operates over.

 A large range of temperatures, voltages, and process corners.

 These issues account for increased power dissipation in SoC (System on

 To design low power SRAM memory cells of different configurations like

 compare their performance parameters like-- Read and write delay.

 Leakage power consumption.

 Static noise margins (during hold, read and write).

 the input voltage we can store the value

 First we applied the input voltage to the

 After the pass transistor gets turn on by the

FIG:-READ WAVEFORM OF 6T SRAM FIG:-WRITE WAVEFORM FIG:-STATIC NOISE MARGINS

 Two cross coupled cmos inverters.

 Factory automation (fa).

 Industrial equipment, and

 The smart grids.

 including high noise immunity due to large noise margins.

 Ability to operate at lower power supply voltage.

 Static power dissipation is small and it is limited by the leakage current.

 High noise margin.

 Large cell size.

 complexity of the CMOS processes.

 Tendency to exhibit 'latch-up' phenomena.

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