INPUT OUTPUT

ORGANIZATION
 Peripheral Devices
• Input output subsystem of computer system provides an efficient
mode of communication between central system and outside system.
• Input and output devices attached to computer are called peripherals.
• Common peripherals are keyboard, monitor, printer, magnetic disks
etc.
• IO devices communicates to and from the device and computer using
alphanumeric characters.
• ASCII(American Standard Code for Information Interchange) is the
standard binary code for the alphanumeric characters.
• ASCII table contains 128 characters
out of which 94 char are printing
and 34 char are non printing.
• 94 Printing characters are:
• 26 uppercase letters A through Z.
• 26 lowercase letters a through z.
• 10 numerals 0 through 9.
• 32 special printable characters like
%, *, @ etc.
• 34 control characters are shown in
the table.
• ASCII is a 7 bit code, but in most
computer they are stored in 8
bit(1 byte).
 Input Output Interface
• Input output interface provides a method for transferring information
between internal storage and external I/O devices.
• I/O interface resolves the differences between CPU and peripherals.
• Key differences are :
• Peripherals are electromechanical and electromagnetic devices, CPU and
memory are electronic devices. Therefore conversion of signals may be required.
• Data transfer rate of peripherals is slower than CPU, therefore a synchronisation
mechanism is needed.
• Data code formats in peripherals are different from as in CPU & memory.
• Operating modes of different peripherals is different from each other and each
must be controlled so as not to disturb operation of others connected to CPU.
I/O Bus and Interface Modules
• As the address is made available in address lines, processor provides I/O
command that is executed in the interface and attached peripheral device.
There are four types of commands processor may issue:
• Control command: issued to activate the peripheral and to inform what to do. Ex.
Magnetic tape unit is instructed to rewind or move forward the tape.
• Status command: used to test various status conditions in the interface and peripherals.
Ex. Computer wish to check the status of a peripheral before a transfer is initiated.
• Output data: It causes interface to transfer data from the bus into peripheral’s register.
Ex. Computer starts the tape moving by issuing a control command. Status of tape is
monitored by status command. When tape is in correct position, the processor issues a
data output command. The interface transfers information from bus to its buffer register
and then buffer register to tape using tape controller.
• Input data: The interface receives data from peripheral and places it in its buffer register.
The processor checks availability of data by means of status command and then issues
data input command. The interface places data on the bus, which is accepted by the
processor.
I/O verses Memory Bus
Isolated verses memory mapped I/O
• Computer use common bus to transfer information between memory
or I/O and CPU.
• CPU specify whether the address on address line is for memory or
interface register.
• I/O read or write control lines are enabled during I/O transfer.
• Memory read or write control lines are enabled during memory
transfer.
• This configuration isolates I/O interface addresses from memory
address and called isolated I/O method.
Isolated verses memory mapped I/O
• In isolated I/O, CPU has distinct I/O instruction, and each instruction is
associated with address of interface register.
• When CPU decodes the I/O instruction, it places associated address
into the common address line and at the same time, it enables I/O read
or write control line.
• This informs external unit that address is for an interface register.
• On the other hand, when CPU fetches memory instruction, it places
memory address on the address line and enables memory read or write
control.
• This informs the external unit that the address is for memory.
Isolated verses memory mapped I/O
• Isolated I/O method uses separate address space of I/O and memory.
• In memory mapped method same address space is used for the both.
• In this case only one set of read and write signals are used for both I/o and
memory. This is called memory mapped I/O.
• CPU treats interface registers as a part of memory system.
• The addresses assigned to interface registers can not be used for memory
words.
• In memory mapped I/O, there is no specific I/O instruction.
• Same instructions are used to manipulate data in memory and I/O interface
registers.
An Example of I/O Interface unit
Asynchronous Data Transfer
Strobe Control
• The strobe control method of asynchronous data transfer employs a
single control line to each transfer.
• Strobe may be initiated by either source or destination unit.
Handshaking
Modes of Transfer
Programmed I/O
Interrupt initiated I/O
Direct Memory Access (DMA)
Input Output Processor (IOP)
 Direct Memory Access (DMA)
The transfer of data between a fast storage device such as magnetic disk and memory is often
limited by the speed of the CPU. Removing the CPU from the path and letting the peripheral
device manage the memory buses directly would improve the speed of transfer. This transfer
technique is called direct memory access (DMA). During DMA transfer, the CPU is idle and has
no control of the memory buses. A DMA controller takes over the buses to manage the
transfer directly between the I/O device and memory.

Figure: CPU bus signals for DMA transfer

 Direct Memory Access (DMA)
• Figure shows two control signals in the CPU that facilitate the DMA transfer. The bus request
(BR) input is used by the DMA controller to request the CPU to relinquish control of the
buses. When this input is active, the CPU terminates the execution of the current instruction
and places the address bus, the data bus, and the read and write lines into a high-impedance
state behaves like an open circuit. The CPU activates the Bus grant (BG) output to inform the
external DMA that the buses are in the high-impedance state. The DMA that originated the
bus request can now take control of the buses to conduct memory transfers without
processor intervention. When the DMA terminates the transfer, it disables the bus request
line. The CPU disables the bus grant, takes control of the buses, and returns to its normal
operation.
• When the DMA takes control of the bus system, it communicates directly with the memory.
The transfer can be made in several ways. In DMA burst transfer, a block sequence consisting
of a number of memory words is transferred in a continuous burst while the DMA controller
is master of the memory buses. This mode of transfer is needed for fast devices such as
magnetic disks, where data transmission cannot be stopped or slowed down until an entire
block is transferred. An alternative technique called cycle stealing allows the DMA controller
to transfer one data word at a time after which it must return control of the buses to the CPU.
The CPU merely delays its operation for one memory cycle to allow the direct memory I/O
transfer to “steal” one memory cycle.
Figure: Block diagram of DMA controller
 Example: Raj K. Pal
R a j K . P a l
01010010 01100001 01101010 00100000
 Input Output Processor (IOP)
• IOP is similar to CPU except that it is designed to handle the IO
processing.
• Unlike DMA controller (that must be setup by CPU), the IOP can fetch
and execute its own instruction.
• Both CPU and IOP exists in the system ,however CPU is the Master
while IOP is the Slave
• The CPU initiates the I/O program after that IOP operates independent
of the CPU.
• The IOP fetches & executes I/O instructions to facilitates I/O transfer, if
required .It can perform all the functions of CPU.
Input Output Processor (IOP)
CPU-IOP
Communication