Ms. K.

Harini
AP/ Department of ECE,
Coimbatore Institute of Technology
III Year, Section –I
Academic Year: 2022-23
 SEQUENTIAL CIRCUITS
• Combinational circuits were designed whose outputs
depend only on the current inputs.
• In Sequential circuits, their outputs depend on both
current and previous inputs.

2
 SEQUENTIAL CIRCUITS
• Unlike conventional circuits, in sequential circuit have very
critical timing issues. One has to be cautious about the timing
analysis or timing of data w.r.t clock or w.r.t each other
• Timing metrics are very important so that no violation as far as
data is concerned
• These circuit works properly if the data’s are fed properly,
processed and take the output at the right time without
compromising the performance of the circuit.
• Using the combinational circuits developed so far, sequential
circuits such as latches and flip-flops can be built. 3
 SEQUENTIAL CIRCUITS
• Sequential circuits have memory which are sometimes called
“Memory Elements” which holds the data called “tokens”
• It helps in distinguishing the current token from the previous or
next token. Thus it is called “Sequencing elements”
• Sequencing elements helps in delaying the tokens that arrives
too early & preventing it from catching up with previous
tokens
• This adds extra delay thus decreases the performance of the
system. This extra delay is called “Sequencing overhead”
4
 Conventional CMOS Latches
Pass Transistor Latch
Φ=1, T= ON

•Pros
Φ=0, T= OFF

+ Compact
+ Fast
•Cons
– backdriving
D Q
– Output is dynamic, i.e output floats when the latch is opaque
– Output does not swing from rail-to-rail (GND to Vdd)
– Output never rise above (Vdd- Vt)

5
 Transmission gate Latch

+ No Vt drop
- Requires inverted
clock D Q


Φ=1, Φ’=0 T= ON
Φ=0, Φ’=1 T= OFF

6
 Inverting buffer Latch
+ Restoring the output
+ No backdriving
– Inverted output

7
Tristate feedback Latch

8
Tristate feedback Latch

9
Buffered Input Latch


X
D Q



+ Output is non-inverting

10
DATAPATH LATCH
 Q
+ smaller/ more compact
+ faster
X
- unbuffered input hence backdriving risk D

BUFFERED OUTPUT 
+ No backdriving
+ Very robust
Tristate feedback
•Widely used in standard cells latch 

- Rather large & slow

- High clock loading  Q

X
D



Buffered input
latch 
11
 Has a slightly lower logical effort
Isolate noise at the
output

However (e) and (f)

introduce output noise
Feedback prevent from
output floating

When input noise is better

controlled it can be used
Very robust transparent because it is faster and more
latch compact

Jamb latch - a weak Jamb latch - used in register

feedback inverter reduces files and FPGA cells
clock load

Latch used in Itanium

Processor

12
Circuit (b) is Logically equivalent to (a) but electrically inferior
because toggling D while the latch is opaque can cause charge
sharing noise on the output node.
 D LATCH
• D latch is transparent when CLK = 1,

meaning Q follows D.
• It becomes opaque when CLK = 0,

meaning Q retains its previous value

& ignores changes in D.

• The D latch is also known as a level-sensitive latch because

the state of the output is dependent on the level of the clock
signal.
• By inverting the control connections to the multiplexer, the
latch becomes negative-level-sensitive 14
CMOS POSITIVE LEVEL SENSITIVE
D LATCH

15
D LATCH

16
EDGE TRIGGERED FLIP FLOPS
• Edge-triggered flip-flop copies D to Q on the rising edge of
CLK and holds its previous value at other times
• By combining two level-sensitive latches, one negative-
sensitive and one positive-sensitive, the edge-triggered flip-flop
are constructed

• The first latch stage is called the

master and the second is called
the slave
17
Positive edge triggered FF

18
 EDGE TRIGGERED FLIP FLOP
• Good design practice would buffer the input and output with
inverters

19
NEGATIVE EDGE FLIP FLOP
• By reversing the latch polarities, a
negative-edge triggered flip-flop may
be constructed. Positive edge
triggered FF
• A collection of D flip-flops sharing a
common clock input is called a
register. A register is often drawn as a
flip-flop with multi-bit D and Q busses
Negative edge
triggered FF
20
Negative edge triggered FF

21
22
NO FLIP-FLOP LATCH
Flip-flop is a bistable device i.e., it
Latch is also a bistable device whose
1 has two stable states that are
states are also represented as 0 and 1.
represented as 0 and 1.
It checks the inputs but changes
It checks the inputs continuously and
the output only at times defined by
2 responds to the changes in inputs
the clock signal or any other
immediately when clock is high.
control signal.
3 It is a edge triggered device. It is a level triggered device.
They are classified into
There is no such classification in
5 asynchronous or synchronous
latches.
flipflops.
It forms the building blocks of These can be used for the designing of
6 many sequential circuits like sequential circuits but are not generally
counters. preferred.
Flip-flop can be build from
8 Latches can be build from gates
Latches
23
9 ex:D Flip-flop, JK Flip-flop ex: SR Latch, D Latch
 Flip-Flop Design
• Flip-flop is built as pair of back-to-back latches
Inverting
buffer latch

buffered input latch datapath latch

24
 RESETTABLE LATCHES AND FLIP-FLOPS
• There are 2 types of reset
i. Synchronous reset
ii. Asynchronous reset
• Asynchronous reset forces Q low immediately, while
synchronous reset waits for the clock.
• Synchronous reset signals must be stable for a setup and hold
time around the clock edge

25
RESETTABLE LATCHES- Synchronous reset

Datapath
latch

Clock Reset D Q

1 0 1 1

0 0 0 1 (previous state)
1 1 1 0

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 Synchronous reset- Case (i)
Clock Reset D Q

1 0 1 1

1 0 1

1
0 0 0 1
1 ON

1
0

OFF

0 27
 Synchronous reset- Case (ii)
Clock Reset D Q

0 0 0 1 (previous state)

Retains
previous state
0 1
0

1
1 0
0 OFF 1
(previous state )

0
1
0
ON

1 28
 Synchronous reset- Case (iii)
Clock Reset D Q
1 1 1 0
Should be made ‘0’
irrespective of D

1 1 0

0
1 1
1 ON

1
0

OFF

0 29
RESETTABLE LATCHES AND FLIP-FLOPS

Resettable Latches

Resettable Flip-flop

Clock=1
Clock=0

Tristate feedback Datapath

latch Clock=1 Clock=0 latch 30
RESETTABLE LATCHES- Asynchronous reset

Clock Reset D Q

1 0 1 1

0 0 0 1 (previous state)
0 1 1 0

1 1 1 0 31
Asynchronous reset- Case (i)
Clock Reset D Q

1 0 1 1

0 1
1

1
0 0 1
ON

1 1
0

OFF

1
0 32
Asynchronous reset- Case (ii)
Clock Reset D Q

0 0 0 1 (previous
state)

0 1
0

1
1 0 Previous
OFF 1
state
0 0
1
0
ON

1
1 33
Asynchronous reset- Case (iii)
Clock Reset D Q

0 1 1 0

1 0
0

0
1 1
OFF

1 0
1
1
ON

0
1 34
Asynchronous reset- Case (iv)
Clock Reset D Q

1 1 1 0

1 0
1

0
1 1
ON

1 1
0

OFF

0
0 35
RESETTABLE LATCHES AND FLIP-FLOPS

Resettable Latches

Resettable FF

Inverting Resettable
Buffer latch latch
36
Flip-flop With Asynchronous Set and Reset
Clock/ D Set= 1 Q= 1
0 or 1 Reset=1 Q=0

37
Flip-flop With Asynchronous Set and Reset
D= 0/ 1 Set= 1 Q= 1
Clock= 0/1 Reset=0

1
0 1 0 1

1
ON
Φ=1

1 0
ON
Φ=0

38
Flip-flop With Asynchronous Set and Reset
D= 0/ 1 Set= 0 Q= 0
Clock= 0/1 Reset=1

0
1 1 0

39
 Exercise- 1

Design a positive level sensitive D latch in which the Q

output by a signal reset may be reset to ‘0’ independent
of the state of the clock signal.

(i.e RESET=1, Q=0)

40
Positive edge triggered D flip-flop with
Asynchronous Reset & clock input

Clock Reset D Q
0 0 1 Previous state
1 0 1 1
0 0 0 Previous state
1 0 0 0
0/1 1 0/1 0 41
 Positive edge triggered D flip-flop with
Asynchronous Reset & clock input
Clock Reset D Q

0 0 1 Previous state

1
1 0
1 0
1 1
OFF
ON
0

1
0 1
OFF ON

0
42
 Positive edge triggered D flip-flop with
Asynchronous Reset & clock input
Clock Reset D Q

1 0 1 1

(Previous
value) 1
1 1
0 1
0 0 1
1
ON
OFF
1

0
1 0
ON OFF

1 43
 Positive edge triggered D flip-flop with
Asynchronous Reset & clock input
Clock Reset D Q

0 0 0 Previous state (1)

Retains in
previous
1 state
1 0
1 1
1 0 1
0 0
OFF
ON
0

1
0 1
0 1
OFF ON
Previous
1 State

0
44
 Positive edge triggered D flip-flop with
Asynchronous Reset & clock input
Clock Reset D Q

1 0 0 0

(Previous
value) 1
1 1 0
0 0
0 1 1
ON
OFF
1

0
1 0
ON OFF

1
45
Positive edge triggered D flip-flop with
Asynchronous Reset & clock input
Clock Reset D Q

0/1 1 0/1 0

0
0
0

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 Exercise- 2

Design a positive edge-triggered D register that can be

asynchronously set Q output to high independent of the
state of the clock signal.

(i.e SET=1, Q=1)

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Positive Edge Triggered Asynchronously
Settable D Flip-flop

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 Exercise- 3

Design a positive edge-triggered D register in which the

Q output may be reset to low in synchronous with the
clock signal.

(i.e RESET=1, Q=0 when Clock=1)

49
Positive Edge Triggered D Flip-flop with
Reset synchronous with clock input

50
 Enabled Latches and Flip-flops
Sequencing elements also often accept an enable input. When en is low, the element
retains its state independently of the clock. This is performed with an input multiplexer
or clock gating.

51
 Incorporating Logic into Latches
• Another way to reduce the sequencing overhead of latches is to replace
some of the inverters in the latch with gates that perform useful
computation.

52
 True Single-phase Clock (TSPC) Latches and
Flip-flops
• TSPC Latches and flip-flops replace the inverter-transmission gate or C 2MOS
stage with a pair of stages requiring only the clock, not its complement.

53
Sequencing Methods

54
Static Sequencing Methods

55
 Timing Diagram
tpd Logic Prop. Delay

tcd Logic Cont. Delay

tpcq Latch/Flop Clk->Q Prop. Delay

tccq Latch/Flop Clk->Q Cont. Delay

tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time

56
 Timing Diagram
• The data must have settled down by some (setup) time before the
rising edge of the clock and should not change again until a
(hold) time after the clock edge.
• The data must be stable for some window around the rising edge
of the clock if it has to be reliably sampled.
• The output begins to change after a clock-to-Q contamination
delay and completely settles after clock-to-Q propagation delay
• The output of the latch initially changes after the clock is applied
and continues to track the input after the D-to-Q delay
• The input D must setup and hold around the falling edge that
defines the end of the sampling period 57
Contamination and Propagation delay

58
 Max delay Constraint
• The entire clock cycle is available for computations in the
combinational logic
• The sequencing overhead of the latches or FF cuts into this time.
• If the combinational logic delay is too great, the receiving
element will miss its set-up time and sample the wrong value. This
is called a setup time failure or max-delay failure
• This is solved by redesigning the logic to be faster or by
increasing the clock period.
• Compute the actual time available for logic and sequencing
overhead of each of the sequencing elements: Flip-flops, 2-phase
latches and pulsed latches. 59
Flip-flops: Max delay Constraint

t pd  Tc  tsetup  t pcq 
     60
sequencing overhead
Two-phase Latch: Max delay Constraint

61
Two-phase Latch: Max delay Constraint
Assume that the path takes no more than a cycle, thus the
cycle time must be

The maximum logical delay is the sum of the logical delay

through each of the two phases; which is the sequencing
overhead;

t pd  t pd 1  t pd 2  Tc  2t  
pdq

sequencing overhead

62
 Pulsed Latch: Max delay Constraint
If the pulse with
is wide enough,
the delay
constraint is
similar to two-
phase latches
assuming only 1
latch in the path

If the pulse
width is
narrow, then
data must be
set before the
pulse rises

63
 Pulsed Latch: Max delay Constraint

𝑇𝑐 ≥ max⁡(𝑡𝑝𝑑𝑞 + 𝑡𝑝𝑑 , 𝑡𝑝𝑐𝑞 + 𝑡𝑝𝑑 + 𝑡𝑠𝑒𝑡𝑢𝑝 − 𝑡𝑝𝑤 )

Thus the maximum logical delay that the sequencing overhead is

just one latch delay if the pulse is wide enough to hide the setup
time;

t pd  Tc  max t pdq , t pcq  tsetup  t pw 

          
sequencing overhead

64
 Min-delay Constraints
• The sequencing elements can also be placed in back-to-back
registers and still functions correctly

• If the hold time is large and the contamination delay is small,

then data can be incorrectly propagated through 2 successive
elements on the clock edge, thus corrupting the state of the
system. This is called a race condition or hold-time failure or
min-delay failure.

• This can only be fixed by redesigning the logic, not by slowing the
clock. 65
Flip-flop: Min-delay Constraint
Min- contamination delay;

tcd  thold  tccq

66
Two-phase latch: Min-delay Constraint

Min- delay for the

first clock cycle
Second clock cycle
Hold time is reduced
by nonoverlap thus
tcd 1,tcd 2  thold  tccq  tnonoverlap
min-delay failure is
avoided completely

67
Pulsed latch: Min-delay Constraint
tcd  thold  tccq  t pw

68
 Time borrowing
• In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, the system fails
– If it arrives early, time is wasted
– Flops have hard edges as they strongly portray the clock cycle
– NO BORROWING
• In a latch-based system
– Data can pass through a latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

69
 Time borrowing

Time borrowing can accumulate

across multiple cycles

A system with feedback

must compensate for the
delay within the cycle

70
 How much Borrowing?

2-Phase Latches: Pulsed Latches:

Tc tborrow  t pw  tsetup
tborrow   tsetup  tnonoverlap  71
2
 Clock skew and Flip-flops
• So far, we have assumed zero clock skew (i.e) ideal clock
with no difference in clock arrival

• Clocks really have uncertainty in arrival time

– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing
– launching FF receives its clock late and receiving FF
receives its clock early (worst scenario for max delay)
– launching FF receives its clock early and receiving FF
receives its clock late (worst scenario for min delay)

72
Clock skew and Flip-flops

t pd  Tc  t pcq  tsetup  tskew 

      
sequencing overhead

tcd  thold  tccq  tskew

73
 Clock skew and transparent latches
• Full cycle is available for computation even when the clocks
are skewed because the data can still arrive at the latches
while they are transparent. Hence, transparent latch-based
systems are skew-tolerant when compared to FFs

74
2-Phase Latches:
t pd  Tc  2t  
pdq

sequencing overhead

tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew

Tc
tborrow   tsetup  tnonoverlap  tskew 
2
Pulsed Latches:
t pd  Tc  max t pdq , t pcq  tsetup  t pw  tskew 
            
sequencing overhead

tcd  thold  t pw  tccq  tskew

tborrow  t pw  tsetup  tskew  75

Sequencing Dynamic Circuit

76
 Traditional Domino Circuit
• Delay of the path is the sum of evaluation delays of each gate
along the path as the entire clock period is divided into two
half-cycles.
• One phase evaluates while the other precharges, then the
other phase evaluates while the first precharges.

Evaluation Precharge

Precharge Evaluation

77
Traditional Domino Circuit

78
Traditional Domino Circuit with clock-skew

• Data must be launched into the first dynamic gate of each cycle on the
rising edge of the clock and must be set-up before the falling edge
• Thus clock-skew must cut into this computation time
• If clock-skew and set-up time are greater than the propagation delay,
then

79
Traditional Domino Circuit- conclusion
• Traditional domino circuits have high sequencing overhead from the latch and have hard edges in
each half-cycle

• The first domino gate does not begin evaluating until the rising edge of the clock but the result must
setup at the latch before the falling edge of the clock

• Thus designers have gone for skew-tolerant domino sequencing techniques by removing the latch to
soften the falling edge and cut the overheads.

80
Eliminating Latches in Skew-tolerant
Domino Circuits

81
 Full Keeper
• The dynamic gate receives correct information if the clocks overlap
• The output of c floats either high or low without a keeper to hold
the data.
• The below circuit shows a full keeper consisting of weak cross-
coupled inverters to hold the output either high or low

82
Skew-tolerant Domino Circuits-
conclusion

83
Time borrowing in Skew-tolerant
Domino Circuits

84
Two-phase skew-tolerant
domino clock generator

85
Opportunistic Time Borrowing (OTB) domino

86
Four-phase skew-tolerant domino

87
Four-phase skew-tolerant
domino clock generator

88