Final

DESIGN OF APPROXIMATE MULTIPLIERS USING LOW ERROR EFFICIENT APPROXIMATE
ADDERS
Index
• Abstract
• Introduction
• Literature review
• Existing Method
• Drawbacks
• Proposed method
• Advantages
• Applications
• Hardware and Software Requirements
• Results
• Conclusion
• Future scope
• References
Abstract
In this project, a methodology for designing approximate multiplier
using low error efficient approximate adders has been proposed. The
proposed methodology utilizes FPGA resources efficiently to reduce the
error of approximate adders. We propose two approximate adders for
FPGAs using our methodology: low error and area efficient approximate
adder (LEADx), and area and power efficient approximate adder
(APEx). Both approximate adders are composed of an accurate and an
approximate part. After that these approximate adders are utilized to in
the reduction stage of Multipliers.
Introduction
Approximate Computing
• To improve speed and power performance

• Efficient paradigm to lower power consumption
• Reduces computational delay in error resilient applications
• Gain Power, Speed and Area advantages
• Decrease the design complexity
Approximate adders
Approximate adders can be broadly classified into the following categories:
segmented adders, divide n-bit adder into several r-bit adders operating
in parallel;
speculative adders, which predict the carry using only the few previous
bits;
approximate full-adder based adders, which approximate the accurate

full-adder at transistor or gate level.
Higher speed and larger areas
 m bit aprroximation
The approximate parts of these adders are designed in a systematic
way to minimize the mean square error (MSE).
 LEADx has lower MSE
APEx has smaller area and lower power consumption than the other
approximate adders than the existing adders.
LEADx provided better quality than the other approximate adders for
video encoding application.
Literature review
S. Journal Authors Title Outcomes

NO Type
1 IEEE G. A. Gillani, MACISH: In this, a more effective quality-efficiency trade-
Transaction( M. A. Hanif, Designing off offered by the ISH methodology as compared
2019) et al. approximate MAC to the conventional approximate computing
accelerators with methodology.Better when compared to error-
internal-self- restricted approximate computing.
healing
2 IEEE E. Kalali and An approximate The proposed approximation technique causes
conference I. Hamzaoglu HEVC intra negligible PSNR loss and bit rate increase. It
(2020) angular prediction significantly reduces area of the proposed
hardware approximate hardware by enabling efficient use
of one MCM data-path to implement all constant
multiplications using add and shift operations
and by reducing amount of on-chip memory.
Existing method
In the existing method, an approximate adder LOA (lower-part OR

adder) is designed. The lower-part OR adder (LOA) is an
approximate adder design implemented using an approximate FA for
the least significant bits (LSBs) of a multi-bit adder.
The LOA consists of two parts: an accurate part and an inaccurate

part. The former part uses a traditional precise adder, such as the
ripple carry adder (RCA) and carry-look-ahead adder (CLA), to
calculate the most significant bits (MSBs) with no computation error.
Whereas, the latter part only uses an OR operation to approximately

obtain LSB summations. Furthermore, the output of an AND
operation for the MSB input pair of the inaccurate part is utilized as a
carry input to the accurate part.
Disadvantages
Accuracy is very low.
Energy consumption is high
Delay increases as the computation time of output increases.

Proposed method
The proposed design methodology uses the approximate fulladder based

n-bit adder architecture shown in Fig. n-bit addition is divided into n-bit
approximate adder in the LSP and (n−m)-bit accurate adder in the MSP.
Breaking the carry chain at bit-position m generally introduces an error

of 2m in the final sum.
For an area efficient FPGA implementation, we propose to split the first

m − 2 bits of LSP into d(m − 2)/2e groupsof 2-bit inputs such that each
Fig: approx. adder
group is mapped to a single LUT.
Proposed Method
AAD1 AAD2
Proposed method
The proposed LEADx approximate

adder is shown in Fig. 5. An n-bit
LEADx uses [(m − 2)/2] copies of AAd2
adder in the least significant m − 2 bits of
the approximate adder architecture. In
LEADx, Cm−2 = Am−3. Fig: LEADx
 AAd2 implements a 5-to-2 logic
function that is mapped to a single LUT.
APEx is also based on the approximate adder architecture shown in Fig. For
the least significant m − 2 bits of the LSP, the aim is to find an approximate
function with no data dependency.
Carry should neither be generated nor used for sum computation. A 1-bit input
pair at any bit position i ≤ (m − 2) should produce a 1-bit sum output only.
In general, any logic function with 1-bit output can be used as an approximate
function to compute the approximate sum of 1-bit inputs at ith bit position. A
constant 0 or constant 1 at the output are also valid approximate functions.
Fixing the output to 0 or 1 will reduce the area and power
consumption of the approximate adder because no hardware will be
required for sum computation.
FIG: APEx
Existing multiplier
Fig: Multiplication process

Proposed multiplier
• Multiplication can be considered as a series of repeated additions. The number to be added is

the multiplicand, the number of times that it is added is the multiplier, and the result is the
product. Each step of addition generates a partial product. In most computers, the operand
usually contains the same number of bits. When the operands are interpreted as integers, the
product is generally twice the length of operands in order to preserve the information content.
• Stage1. Multiply (or better expressing, AND) each bit of multiplicand by each bit of
multiplier, yielding n2 partial products.
• Stage2. Reduce the number of partial products
using the layers of a FA and a HA blocks.
• Stage3. Adding two n-sets resulted from the

previous stage to an n-bit adder. It should be noted
that the second stage is carried out as follows.
• Here for a 8 bit multiplier our proposed adders can

be implemented to reduce the partial products. It
can be shown as below.
Approximate Multiplier
 A distinguishing feature of the proposed approximate
multiplier is the simplicity to use approximate adders in
the partial product accumulation
 In the proposed design, the simplification of the partial
product accumulation stage is accomplished by using an
adder tree, in which the number of partial products is
reduced by a factor of 2 at each stage of the tree.
 This adder tree is usually not implemented using accurate
multi-bit adders due to the long latency. However, the
proposed approximate adder is suitable for implementing
an adder tree, because it is less complex than a
conventional adder and has a much shorter critical path
delay
Advantages
Computational delay is reduced
Improvement in accuracy of output is achieved
Area and Energy consumption are optimized.

Applications
 Digital signal processors
Digital image processors
Video processor applications
MAC & Arithmetic circuits

Hardware and Software Requirements
 Software: Xilinx ISE 14.7
 HDL: Verilog
RESULTS
RTL SCHEMATIC TECHNOLOGY SCHEMATIC

SIMULATION RESULTS
•
Conclusion
• In this paper, two low error efficient approximate adders for FPGAs are proposed, where
approximation is done only in the LSP and the MSP is kept accurate. The first approximate adder,
LEADx, achieves better area and delay compared to exact adder implementations. The second
approximate adder, APEx, has reduced area, and less power consumption than the existing adders. It
has smaller area and lower power consumption than the other approximate adders in the literature.
Therefore, the proposed approximate adders can be used for FPGA implementations of error tolerant
applications. The proposed adders can be designed efficiently by establishing a trade-off between
error and parameters like area, delay and power by making efficient ways in carry chain or accurate
adders etc. and as an application it can also be implemented in multiplier architectures at the partial
product reduction process thereby improving the efficiency of the design.
References
• [1] G. A. Gillani, M. A. Hanif, B. Verstoep, S. H. Gerez, M. Shafique, and A. B. J. Kokkeler,

‘‘MACISH: Designing approximate MAC accelerators with internal-self-healing,’’ IEEE
Access, vol. 7, pp. 77142–77160, 2019.
• [2] E. Kalali and I. Hamzaoglu, ‘‘An approximate HEVC intra angular prediction hardware,’’
IEEE Access, vol. 8, pp. 2599–2607, 2020.
• [3] T. Ayhan and M. Altun, ‘‘Circuit aware approximate system design with case studies in
image processing and neural networks,’’ IEEE Access, vol. 7, pp. 4726–4734, 2019.
• [4] W. Ahmad and I. Hamzaoglu, ‘‘An efficient approximate sum of absolute differences
hardware for FPGAs,’’ in Proc. IEEE Int. Conf. Consum. Electron. (ICCE), Las Vegas, NV,
USA, Jan. 2021, pp. 1–5.
• [5] H. Jiang, C. Liu, L. Liu, F. Lombardi, and J. Han, ‘‘A review, classification, and
comparative evaluation of approximate arithmetic circuits,’’ ACM J. Emerg. Technol. Comput.
Syst., vol. 13, no. 4, pp. 1–34, Aug. 2017.

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DESIGN OF APPROXIMATE MULTIPLIERS USING LOW ERROR EFFICIENT APPROXIMATE

• To improve speed and power performance

Approximate adders can be broadly classified into the following categories:

approximate full-adder based adders, which approximate the accurate

Higher speed and larger areas

 LEADx has lower MSE

S. Journal Authors Title Outcomes

In the existing method, an approximate adder LOA (lower-part OR

The LOA consists of two parts: an accurate part and an inaccurate

Whereas, the latter part only uses an OR operation to approximately

Accuracy is very low.

Energy consumption is high

Delay increases as the computation time of output increases.

The proposed design methodology uses the approximate fulladder based

Breaking the carry chain at bit-position m generally introduces an error

For an area efficient FPGA implementation, we propose to split the first

The proposed LEADx approximate

Fig: Multiplication process

• Multiplication can be considered as a series of repeated additions. The number to be added is

• Stage3. Adding two n-sets resulted from the

• Here for a 8 bit multiplier our proposed adders can

multiplier is the simplicity to use approximate adders in

the partial product accumulation

 In the proposed design, the simplification of the partial

product accumulation stage is accomplished by using an

adder tree, in which the number of partial products is

reduced by a factor of 2 at each stage of the tree.

 This adder tree is usually not implemented using accurate

multi-bit adders due to the long latency. However, the

proposed approximate adder is suitable for implementing

an adder tree, because it is less complex than a

conventional adder and has a much shorter critical path

Computational delay is reduced

Improvement in accuracy of output is achieved

Area and Energy consumption are optimized.

 Digital signal processors

Digital image processors

Video processor applications

MAC & Arithmetic circuits

 Software: Xilinx ISE 14.7

RTL SCHEMATIC TECHNOLOGY SCHEMATIC

• [1] G. A. Gillani, M. A. Hanif, B. Verstoep, S. H. Gerez, M. Shafique, and A. B. J. Kokkeler,

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