Flip-Flops and Latches

PLTW Engineering

Digital Electronics
Activity 3.1.1 Sequential Logic D Flip-Flop and JK Flip-Flop

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 Flip-Flops and Latches
Presentation topics:
Review sequential logic and the flip-flop
Introduce the D flip-flop and provide an excitation table
and a sample timing analysis
Introduce the J/K flip-flop and provide an excitation table
and a sample timing analysis
Review flip-flop clock parameters
Introduce the transparent D-latch
Discuss flip-flop asynchronous inputs

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 Sequential Logic & The Flip-Flop

Inputs . . Outputs
. Combinational .
Logic Gates

Memory Elements
(Flip-Flops)
Clock

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 D Flip-Flop: Excitation Table

D CLK Q Q
D Q
0  0 1
1  1 0
CLK Q
 : Rising Edge of Clock

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 D Flip-Flop: Example Timing

Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0 Q=D=0

No Change No Change No Change

CL
K

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 J/K Flip-Flop: Excitation Table

J K CLK Q
J Q
0 0  Q0 No Change
CLK
0 1  0 Clear
K Q
1 0  1 Set

1 1  Q0 Toggle

 : Rising Edge of Clock

Q : Complement of Q

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 J/K Flip-Flop: Example Timing

NO NO
SET TOGGLE TOGGLE CLEAR CHANGE SET CHANGE
Q

CL
K

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 Clock Edges

Rising Edge
Positive Edge Transition

Falling Edge
Negative Edge Transition

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 POS & NEG Edge Triggered D
Positive Edge Trigger
D CLK Q Q
D Q
0  0 1
1  1 0
CLK Q
 : Rising Edge of Clock

Negative Edge Trigger

D CLK Q Q
D Q
0  0 1
1  1 0
CLK Q
 : Falling Edge of Clock

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 POS & NEG Edge Triggered J/K
Positive Edge Trigger
J K CLK Q
J Q 0 0  Q0

CLK
0 1  0
1 0  1
K Q
1 1  Q0
 : Rising Edge of Clock
Negative Edge Trigger
J K CLK Q
J Q 0 0  Q0

CLK
0 1  0
1 0  1
K Q
1 1  Q0
 : Falling Edge of Clock

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 Flip-Flop Timing
1
Data Input
(D,J, or K)
0

tS tH
Setup Time Hold Time
Positive 1
Edge
Clock 0

Setup Time (tS): The time interval before the active transition of the clock signal
during which the data input (D, J, or K) must be maintained.

Hold Time (tH): The time interval after the active transition of the clock signal
during which the data input (D, J, or K) must be maintained.

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 Asynchronous Inputs
Asynchronous inputs (Preset & Clear) are used to
override the clock/data inputs and force the outputs to a
predefined state. PR

The Preset (PR) input forces the output to: D Q

Q 1 & Q  0
The Clear (CLR) input forces the output to: CLK Q
CLR
Q  0 & Q 1
PR CLR CLK D Q Q
PRESET CLEAR CLOCK DATA

1 1  0 0 1
1 1  1 1 0
0 1 X X 1 0 Asynchronous Preset
1 0 X X 0 1 Asynchronous Clear
0 0 X X 1 1 ILLEGAL CONDITION

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 D Flip-Flop: PR & CLR Timing

Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0

Clocked Clocked Clocked Clocked Clocked Clocked

Q
Q=1 Q=1
Preset Preset

PR Q=0
Clear

CLR

CLK

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 Transparent D-Latch

EN D Q Q
D Q Q0
0 X Q0

1 0 0 1
EN Q 1 1 1 0

EN: Enable

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 Transparent D-Latch: Example

“Latched” “Transparent” “Latched” “Transparent” “Latched” “Transparent”

Q=0 Q=D Q=1 Q=D Q=0 Q=D

EN

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 Flip-Flop Vs. Latch
The primary difference between a D flip-flop and D latch is
the EN/CLOCK input
The flip-flop’s CLOCK input is edge sensitive, meaning the
flip-flop’s output changes on the edge (rising or falling) of the
CLOCK input
The latch’s EN input is level sensitive, meaning the latch’s
output changes on the level (high or low) of the EN input

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 Flip-Flops and Latches

74LS74
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear, and Complementary Outputs

74LS76
Dual Negative-Edge-Triggered J-K Flip-Flops with
Preset, Clear, and Complementary Outputs

74LS75
Quad Latch

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 74LS74: D Flip-Flop

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 74LS76: J/K Flip-Flop

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 74LS75: D Latch

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