05 Unit V DTE

Rayat Shikshan Sanstha’s
KARMAVEER BHAURAO PATIL

POLYTECHNIC,
SATARA
Data Converters &
PLDs
Department Of Electronics And
Telecommunication Engineering
Digital Techniques
EJ3I Subject Code: 22320 Second Year EJ
Amit Nevase
Lecturer,
Department of Electronics & Telecommunication Engineering,
Karmaveer Bhaurao Patil Polytechnic, Satara
9/16/2018 Amit Nevase 2

Programme Educational Objectives (PEOs)
 PEO 1. Provide socially responsible, environment friendly
solutions to Electronics and Telecommunication
engineering related broad-based problems adapting
professional ethics.
 PEO 2. Adapt state-of-the-art Electronics and
Telecommunication engineering broad-based technologies
to work in multi-disciplinary work environments.
 PEO 3. Solve broad-based problems individually and as a
team member communicating effectively in the world of
work.
Programme Outcomes (POs)
 PO 1. Basic knowledge: Apply knowledge of basic mathematics, sciences and basic
engineering to solve the broad-based Electronics and Telecommunication engineering
problems.
 PO 2. Discipline knowledge: Apply Electronics and Telecommunication engineering

knowledge to solve broad-based Electronics and Telecommunications engineering
related problems.
 PO 3. Experiments and practice: Plan to perform experiments and practices to use the
results to solve broad-based Electronics and Telecommunication engineering
problems.
 PO 4. Engineering tools: Apply relevant Electronics and Telecommunications

technologies and tools with an understanding of the limitations.
 PO 5. The engineer and society: Assess societal, health, safety, legal and cultural
issues and the consequent responsibilities relevant to practice in field of Electronics
and Telecommunication engineering.

Programme Outcomes (POs)
 PO 6. Environment and sustainability: Apply Electronics and
Telecommunication engineering solutions also for sustainable development
practices in societal and environmental contexts.
 PO 7. Ethics: Apply ethical principles for commitment to professional ethics,

responsibilities and norms of the practice also in the field of Electronics and
Telecommunication engineering.
 PO 8. Individual and team work: Function effectively as a leader and team

member in diverse/ multidisciplinary teams.
 PO 9. Communication: Communicate effectively in oral and written form.
 PO 10. Life-long learning: Engage in independent and life-long learning

activities in the context of technological changes also in the Electronics and
Telecommunication engineering and allied industry.
Programme Specific Outcomes (PSOs)
 PSO 1. Electronics and Telecommunication

Systems: Maintain various types of Electronics
and Telecommunication systems.
 PSO EDA Tools Usage: Use EDA

2.
tools to simple
develop
Electronics
Telecommunication and circuits.
engineering related

Course Outcomes
 Use number system and codes for interpreting working

of Digital System.
 Use Boolean Expressions to realize the logic circuits.
 Build simple combinational circuits.
 Build simple sequential circuits.
 Test data converters and PLDs in digital

electronics systems.

Teaching & Examination Scheme
Tota
l Examination Scheme
Teachin Cred
g its
Scheme (L+T Theory Marks Practical Marks
+P)
L T P C ESE PA Total ESE PA Total

Pap
er
Hrs.
Max Min Max Min Max Min Max Min Max Min Max Min
04 -- 02 06
3 70 28 30 00 100 40 25# 10 25 10 50 20

Passing Criterion for Theory Course
 Each Theory course consists of 2 components, ESE (End Semester
Examination) and PA (Progressive Assessment)
 The passing criterion for each theory course is obtaining minimum
40% of marks allotted to ESE & PA component together. [i.e. for total
marks of ESE (70 marks) + PA(30 marks) together = (Total 70+30 =100),
obtaining minimum 40 marks are mandatory for passing the Theory
course.]
 To qualify for above condition (i), obtaining minimum 40% of marks
allotted to ESE component is mandatory. [i.e. for total marks of ESE =
70, obtaining minimum 28 marks are mandatory. For passing ESE
component)

Specification table for Question Paper
Distribution of Theory Marks

Unit Teaching
No. Unit title Hours
Total
R Level U Level A Level Marks
I Number System and Codes 06 2 2 4 08
II Logic Gates and Logic Families 10 4 4 4 12
III Combinational Logic Circuits 16 4 6 8 18
IV Sequential Logic Circuits 16 4 6 8 18
V Data Converters and PLDs 16 4 4 6 14
Total 64 18 22 30 70
Legends: R=Remember, U=Understand, A = Apply and above
Unit I – Number System and Codes
 Number System: Base or radix of number
systems, Binary, Octal, Decimal and Hexadecimal
number system.
 Binary arithmetic: Addition, Subtraction, Multiplication,
Division.
 Subtraction using 1’s complement and 2’s complement
 Codes: BCD, Gray Code, Excess-3, ASCII code
 BCD Arithmetic: BCD Addition

Unit II – Logic Gates & Logic Families
 Logic Gates: Symbol, diode/transistor switch circuit and logical
expression, truth table of basic gates (AND, OR, NOT), Universal
gates (NAND, NOR) and special purpose gates (Ex-OR, Ex-NOR),
Tristate Logic.
 Boolean Algebra: Laws of Boolean algebra, Duality Theorem, De-
Morgan’s Theorem
 Logic Families: Characteristics of Logic families: Noise Margin,
Power Dissipation, Figure of merit, Fan in and Fan out, Speed of
operation, Comparison TTL, CMOS, Types of TTL NAND gate.

Unit III – Combinational Logic Circuits
 Standard Boolean representation: Sum of Product (SOP) &
Product of Sum (POS), Maxterm and Minterm , Conversion
between SOP and POS forms, realization using NAND/NOR gates.
 K-map reduction technique for the Boolean expression:
Minimization of Boolean functions up to 4 variables (SOP & POS
form)
 Design of Airthmetic circuits and code converter using K-map:
Half and Full Adder, Half and Full Subtractor, Gray to Binary and
Binary to Gray Code Converter (up to 4 bit).

Unit III – Combinational Logic Circuits
 Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD Adder
 Encoder/Decoder: Basics of Encoder, decoder, comparison, (IC

7447) BCD to 7- Segment decoder/driver.
 Multiplexer and Demultiplexer: Working, truth table and
applications of Multiplexers and Demultiplexers, MUX tree, IC
74151 as MUX, DEMUX tree, DEMUX as decoder, IC 74155 as
DEMUX
 Buffer: Tristate logic, Unidirectional and Bidirectional buffer (IC
74LS244 and IC 74LS245)

Unit IV – Sequential Logic Circuit
 Basic Memory Cell: RS Latch- using NAND & NOR.
 Triggering Methods: Edge Trigger & Level Trigger.
 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,
Drawbacks of SR FF
 JK Flip Flops: Clocked JK FF with preset & clear, Race around
condition in JK FF, Master Slave JK FF, D and T type Flip Flop,
Excitation Tables of Flip Flops, Block schematic and function table
of IC 7474, IC 7475.
Unit IV – Sequential Logic Circuit
 Shift Register: Logic diagram of 4 bit shift registers - SISO, SIPO,
PIPO, PISO, 4 Bit Universal Shift Registers.
 Counters: Asynchronous Counter: 4 bit Ripple Counter, 4 Bit
Up/Down Counter, Modulus of counter, Synchronous Counter:
Design of 4 bit Synchronous up/down counter. Decade Counter:
Block schematic of IC 7490, IC 7490 as MOD-N Counter, Ring
Counter and Twisted Ring Counter

Unit V – Data Converters and PLDs
 Data Converters: DAC: Types, weighted resistor circuit and R-2R
Ladder circuit, DAC IC 0808 specifications, ADC: Block diagram,
types and working of Dual Slope ADC, SAR ADC, ADC IC
0808/0809 specification
 Memory: RAM and ROM basic building blocks, read and write
operation, types of semiconductor memories.
 PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
 CPLD: Basic building blocks and functionality.

Unit-V
Data Converters & PLDs

Unit Outcomes
 Calculate the output voltage of the R-2R ladder for the given
specified digital input.
 Calculate the output voltage of Weighted Resistor DAC for the
given specified digital input.
 Explain with sketches the working principle of the given type
of ADC.
 Explain with sketches the working principle of the given types
of memories.
 Explain with basic block diagram the working of the
given type of Programmable Logic Devices.

Introduction
 An analog quantity is one that can take on any value over a

continuous range of values. It represents an exact value.
 Most physical variables are analog in nature. Temperature,
pressure, light, sound intensity, position, rotation and
speed etc. are examples of analog quantities.
 The digital quantity takes on only discrete values. The
value is expressed in a digital code such as a binary or BCD
number.

Necessity of Converters
 When a physical process is monitored or controlled by
a digital system such as a digital computer, the physical
variables are first converted into electrical signal using
transducers and then these electrical analog signals
are converted into digital signals using Analog to
Digital Converters (ADC).

Necessity of Converters
 These digital signals are processed by digital computer
and the output of the digital computer is
converted into analog signals using Digital to Analog
Converters
(DAC).
 The output of DAC is modified by an actuator and the
output of actuator is applied

9/16/2018 Amit Nevase as the control variable. 23
Interfacing a digital system to the analog word
Electrical
Analog
Analog
Output
Bit 1 Bit 1 Output
Bit 2 Bit 2
Bit 3 Bit 3
…………….……..
…………….……..
To control
Physical n-bit Digital n-bit Variable
Transduce
Variabl
e
r
ADC Syste DAC
m Actuator
Bit n-1 Bit n-1
Bit n Bit n
Digital Digital
Inputs
9/16/2018 Amit Nevase Inputs 24
Types of Data Converters
Data Converters
Analog to Digital Digital to Analog

Converter Converter
R-2R Ladder
Counter Type ADC
Type DAC
Tracking Type ADC
Flash Type ADC

Weighted
Single Slope ADC Resistor
Type DAC
Dual Slope ADC
Successive Approximation ADC


Digital to Analog Conversion (D/A)
 Basically, D/A conversion is the process of converting a
value represented in a digital code, such as straight
binary or BCD, into a voltage or current which is
proportional to the digital value.

Digital to Analog Conversion (D/A)
MSB
D
C Vout
Digital Inputs DAC Analog Output
B
 Each of Athe digital inputs A, B, C, and D can assume a value 0 or

L
a 1, S
therefore, there are 24=16 possible combinations of inputs.
B
 For each input number 0000, 0001, ………,1111, the D/A
converter outputs a unique value of voltage. The analog output
voltage Vout is proportional to the input binary number, that is
Analog Output = K X Digital Input
Where, K is the proportionality factor and constant value for a given DAC.

Types of DACs
 Weighted Resistor DAC
 R-2R Ladder Type DAC


Binary Weighted Resistor DAC
 Utilizes a summing op-amp circuit
 Weighted resistors are used to distinguish each
bit from the most significant to the least significant
 Transistors are used to switch and

Vref
between
ground (bit high or low)

(MSB) R Rf
D3
2R +VCC
D2 -
4R Vo
+
D1
-VEE
8R
D0
(LSB)

Rf
R1 +VCC
Vin -
Vo
+
-VEE
Vo=-(Rf/R1).Vin
(Inverting operational amplifier configuration)

Rf
R1 If +VCC
Vin
Iin V1 Ib
- Vo
+
-VEE
Vo=-Iin.Rf

(MSB) R I1 Rf
D3
+VCC
2R I2
D2 -
Iin V1 Vo
4R I3
+
D1
-VEE
8R I4
D0
(LSB)
Output voltage for inverting amplifier is given
by,
V 0  IinRF
But for above circuit,
Iin  (I 1  I 2  I
3  I 4)
Therefore, output voltage for above circuit is

given by,
V 0  (I 1  I 2  I 3  I
4 )R F
From given circuit, (D1 V

(D3 V (D 2 V I3 (D 0 V 1)
I1  I 2 1) 4R I 4
1) R 1) 2R
 8R
But according to Virtual ground concept, V1=0,
Therefore,
D3 D2 D1
I1  I 2 I3 D0
R 2R I 4  8R
Substitute,
4R
D3 D 2  D1 D0
V 0  (   )RF
R 2R 4R
Taking R common 8R
D 2 D1 D 0 R F
V 0  (D3    )( )
2
Advantages:
 Simple Construction/Analysis
 Fast Conversion

Disadvantages:
 Requires large range of resistors (2000:1 for 12-bit
DAC) with necessary high precision for low
resistors
 Requires low switch resistances in transistors
 Can be expensive. Therefore, usually limited to 8-

bit resolution.


R-2R Ladder DAC
+VCC
-
R R R
+
-VEE
Vou
2R 2R 2R 2R 2R
t
(LSB) (MSB)
D0 D1 D2 D3
Digital Inputs

R-2R Ladder DAC
Only one source will be active at a time (using superposition theorem)
i.e. D3 active
R R
2R 2R 2R 2R 2R
Vou
t
D0 D1 D2 D3 (MSB)
(LSB)
+E
Req=2R
Req
=2R 2R Vou
2R Vou  E( 2R ) 
t +E E
2R  2R
t
2
+E
R-2R Ladder DAC
i.e. D2 active
R R
2R 2R 2R 2R 2R
Vou
t
D0 D1 D2
(LSB) D3 (MSB)
+E
R
Req=2R R
Req RTH
=2R 2R 2R Vout
+E 2R
+E
R-2R Ladder DAC
Thevenins equivalent
2R R 2R
RTH
VTH  i1  2R E
E 2
+E
i1 2R VTH  2
RTH  [(2R 2R)  R] 
2R
Req=2R
E 2 E
VTH  2R E
2 Vout  ( R )
2 2R  2R
4

R-2R Ladder DAC
Only one source will be active at a time (using superposition principal)
i.e. D1 active
R R
2R 2R 2R 2R 2R
Vou
t
D0 D1 D2
(LSB) D3 (MSB)
+E
R R
Req
=2R 2R 2R 2R Vou
t
+E
R-2R Ladder DAC
Loop Current method
2R R R 2R
RTH
VTH  i2  2R E
E 4
+E
i1 2R i2 2R VTH  4
RTH  2R)  2R]  R 

[((2R R) 2R
Req=2R
E 2 E
VTH  2R E
4 Vout  ( R )
4 2R  2R
8

R-2R Ladder DAC
i.e. D0 active
R R
2R 2R 2R 2R 2R
Vou
t
(LSB) D0 D1 D2
D3 (MSB)
+E
2R R R R
RTH
+E 2R i 2R 2R
i1 2 i3 VTH

R-2R Ladder DAC
Thevenins equivalent and Loop Current method
2R
E
E VTH  i3  2R 
VTH 8
8
 RTH  [{(((2R 2R)  2R)  R}2R]  R 
R) 2R
Req=2R
E 2 E
VTH  2R E
8 Vout  ( R )
8 2R  2R
16

R-2R Ladder DAC
+VCC
-
R R R
+
-VEE
2R 2R
Vou
2R 2R 2R
t
(LSB) (MSB)
D0 D1 D3
D2
Digital Inputs
Using Superposition Principle, E E E E
Vo u t  2   4
8
D2 D1 D0
2  4  8 1 6 1 6
D 3
R-2R Ladder DAC
Advantages:
 Only two values of resistors are used; R and 2R.
 The actual value used for R is relatively less
important as long as extremely large values, where
stray capacitance enter the picture, are not employs
only ratio of resistor values is critical.

R-2R Ladder DAC
Advantages:
 R-2R ladder network are available in monolithic
chips,. These are laser trimmed to be within 0.01%
of the desired ratios.
 The staircase voltage is more likely to be monotonic
as the effect of the MSB resistor is not many times
grater than that for LSB resistor.

R-2R Ladder DAC
Disadvantages:
 Lower conversion speed than binary weighted DAC

Comparison of Weighted R & R-2R Ladder
Weighted Resistor DAC R-2R Ladder Type

DAC
1. Simple Construction 1. Slightly Complicated

2. Wide range of resistors are Resistors of two values are
2. required required
3. One resistors per bit are Two resistors per bit

3. required are required
4. Noteasy to expand for Easy to expand for

4. more number of bits more number of bits

Specifications of DAC
Resolution:
 Resolution of a DAC is defined as the smallest change that can occur in
an analog output as a result of a change in the digital input.
 The resolution of DAC is also defined as the reciprocal of the number
of discrete steps in the full scale output of DAC.
 The resolution is always equal to the weight of the LSB and is also
referred to as the step size.
step size
% Re solution  full scale 100

Accuracy:
 It is a measure of the difference between actual output
and expected output.
 It is expressed as a percentage of the maximum output
voltage.

Linearity:
 Linearity means that equal increments in digital input of D/A converter
should result in equal increment in analog output voltage.
 If the values of resistance are very accurate and the other components are
also ideal, there would be perfectly liner relation between output and input
and output-input graph would be a straight line.
 Because of the fact that resistances used in the circuit have some tolerances,
perfectly linear of the fact that resistance used in the circuit have some
tolerance, perfectly linear relation between input and output is not obtained.
A special case of liner error is offset error which is the output voltage when
digital input is 0000.

Linearity:
Linearity (Ideal) Non-Linearity
a a
n n
Analog Output Signal
Analog Output Signal

g g
Si Si
t t
tp tp
u u
O O
u u
lo lo
g g
a a
A 0000 0001 0010 0011 0100 0101 A 0000 0001 0010 0011 0100 0101
n 0000 0001 0010 0011
Digital Input Signal 0100 0101 n 0000 0001 0010 0011
Digital Input Signal 0100 0101
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 0
Monotonicity:
 A DAC is said to be monotonic if its output increases as the

binary input is incremented from one value to the next.
 This means that the staircase output will have

no downward steps as the binary input is incremented
from
to full0scale value.
 The DAC is said to be non-monotonic, its

output
if decreases when the binary input is
incremented.
Settling Time:
 When the input signal charges, it is desirable that analog output

signal should immediately show the new output value.
 However, in actual, the D/A converter takes sometimes to settle

at the output voltage.
 Setting time is defined as the time taken by the D/A converter to

1
settle with  LSB of its final value when a change in
input 2
digital signal occurs.
Settling Time:

Temperature Sensitivity:
 The reference voltage supplies and resistors of a D/A converter are all
temperature sensitive.
 Therefore, the analog output voltage depends, at least to some extent,
on temperature.
 The temperature sensitivity of the offset voltage and the bias current
of op-amp also affect the output voltage. The range of temperature
sensitivity for D/A converter is from about  50 to  1.5 ppm*/0C.

Speed:
 Rate of conversion of a single digital input to its analog
equivalent
 Conversion rate depends on
- clock speed of input signal
- settling time of converter
 When the input changes rapidly, the DAC

conversion speed must be high.
Reference Voltages:
 Used to determine how each digital input will
be assigned to each voltage division
 Types:
- Non-multiplier DAC: Vref is fixed
- Multiplier DAC: Vref provided by external source

Offset Voltage:
 Ideally, the output of a DAC should be zero when the
binary input is zero.
 In practice, however, there is a very small
output voltage under this situation called the “Offset
Voltage”
 This offset error, if not corrected, will be added to the
expected DAC output forAmitallNevase

9/16/2018
input cases. 64
Offset Voltage:
Output Voltage
Ideal Output
Digital Input

Applications of DAC
 Digital Motor Control
 Computer Printers
 Sound Equipment (e.g. CD/MP3 Players, etc.)
 Electronic Cruise Control
 Digital Thermostat


IC DAC
 D/A converters, as well as sample and hold amplifiers,
are readily obtainable commercial products.
 Each unit is constructed in a single package; general
purpose economy units are available with 6, 8,10, and
12 bit resolution and high resolution units with up to
16 bit resolution are available.

IC DAC 0808
 An expensive and very popular D/A converter is the
DAC 0808, an 8 bit D/A converter available from
National Semiconductor.
 Motorola manufactures an 8 bit D/A converter, the
MC1508/1408.

IC DAC 0808
Features:
 Relative Accuracy: ± 0.19% error maximum
 Full Scale Current match: ± 1 LSB (typically)
 Fast settling time: 150ns (typically)
 Non-inverting Digital inputs are TTL and CMOS compatible
 High speed multiplying input slew rate: 8mA/µs
 Power Supply Voltage Range: ± 4.5 V to ± 18 V
 Low Power Consumption: 33mW@ ± 5V.

IC DAC 0808
Pin Configuration:

IC DAC 0808
Circuit Diagram:

IC DAC 0808
 A DAC 0808 is connected to provide a full scale output

voltage of Vo=+10Vdc when all 8 digital inputs are 1s
(HIGH).
 If the digital inputs are all 0s (LOW), the output voltage
will be Vo=0Vdc.
 First of all, two dc power supply voltages are required
for the DAC0808: VCC = +5Vdc and VEE = -15Vdc.
 The 0.1µF capacitor is to prevent unwanted
circuit oscillations, and to isolate any variations in VEE.
IC DAC 0808
 Pin 2 is ground (GND), and pin is also referenced to

ground through resistor.
 The output pin 4 is designed to provide an output
current Io. The minimum current (all the digital inputs
low) is 0.0mA and the maximum current (all digital
inputs High), is Iref.

IC DAC 0808
Output Equation:
A1 A2 A3 A4 A5 A6 A7
Vo  Vref (       A8
2 4 8 16 32 64 )
128 256


Analog to Digital Conversion (A/D)
 Analog to digital converter (ADC) produces a digital
output that is proportional to the value of the input
analog signal.
 When an analog signal is processed by a digital system,
an ADC is used to convert the analog voltage to a
digital form suitable for processing by a digital system.

What is Analog to Digital Conversion?
 ADC (Analog to Digital Converter) is an electronic device that

converts a continuous analog input signal to discrete digital
numbers (binary)
 Analog
– Real world signals that contain noise
– Continuous in time
 Digital
– Discrete in time and value
– Binary digits that contain values 0 or 1

What is Analog to Digital Conversion?

Why Analog to Digital Conversion (A/D) important?
 All microcontrollers store information using digital logic
 Compress information to digital form for efficient storage
 Medium for storing digital data is more robust
 Digital data transfer is more efficient
 Digital data is easily reproducible
 Provides a link between real-world signals and data storage

How ADC Works?
Three Stages:
 Sampling
 Quantizing
 Encoding

Sampling
In Sampling, the amplitude of the analog signal is

sampled regularly at uniform intervals, and each
sample is quantized to the nearest value within a range
of digital steps.

Quantizing
ADCs sample the input signal and then apply a process
called Quantization. The quantized forms of the
samples are then converted to binary digits and are
outputted in the form of 1's and 0's.

Quantizing
Output Discrete Voltage

Example: States Ranges (V)
0 0.00-1.25
You have 0-10V signals.
1 1.25-2.50
Separate them into a set
2 2.50-3.75
of discrete states with 3 3.75-5.00
1.25V increments. 4 5.00-6.25
5 6.25-7.50
6 7.50-8.75
7 8.75-10.0

Quantizing
The number of possible states that the converter can output is:
N=2n
where n is the number of bits in the AD converter
Example:
For a 3 bit A/D converter, N=23=8.
Analog quantization size:
Q=(Vmax-Vmin)/N = (10V –
0V)/8 = 1.25V

Encoding
Output Output Binary Equivalent

 Here we assign
States
the
digital value (binary 0 000
number) to each 1 001

2 010
state for the
3 011
computer to read.
4 100
5 101
6 110
7 111

Types of ADC
 Flash ADC
 Delta-Sigma ADC
 Single Slope ADC
 Dual Slope (integrating) ADC
 Successive Approximation ADC


Control Single Slope ADC
Osc
CLK
Analog
+
I/p
-
Counter Counter Counter
Ramp
Generator
RESET
Control Flip Flop Flip Flop Flip
Latch Latch Flop
Circuit Latch
Manual STROBE
Switch
7-Segment 7-Segment 7-
Control Decoder Decoder Segment
Decoder

1 Conversion Cycle
Manual
RESET
t
VA
Ramp
Signal
t
0 t1 t2
Vc
t
Clk
t
Strobe
t
RESET
t
1 Conversion Cycle
Manual
RESET
t
Ramp VB
Signal
t
0 t1 t2
Vc
t
Clk
t
Strobe
t
RESET
t
Single Slope ADC
Advantages:
 Linear conversion from voltage to time or frequency.
 The output is affected by any sudden changes.
 High accuracy

Single Slope ADC
Limitations:
 The comparators are assumed to be perfect i.e. their
gain is infinite and offset zero. It is practically impossible
 This A/D converter cannot take bipolar signals. This difficulty can
be overcome by some modifications.
 Any noise of zero means, riding the input analog signal is not
rejected by system.

Analog
I/p Dual Slope ADC
C
R Comparator
-
+
+
- Counter Counter Counter
Integrator
Vref Clk Osc
RESET Flip Flop Flip Flop Flip

Latch Flop
Control Latch
Latch
Switch Circuit STROBE
Control
7-Segment 7-Segment 7-
Decoder Decoder Segment
Decoder

Dual Slope ADC
 The sampled signal charges a capacitor for a fixed amount of
time
 By integrating over time, noise integrates out of the conversion
Vin
tFIX tmeas t
 Then the ADC discharges the capacitor at a fixed rate with the
counter counts the ADC’s output bits. A longer discharge time
results in a higher count

Dual Slope ADC
Advantages:
 Input signal is averaged
 Greater noise immunity than other ADC types
 High accuracy
 Low cost
 Offset correction can be introduced by a relatively simple circuit,
facilitating auto zeroing.

Dual Slope ADC
Disadvantages:
 Long conversion time as compare with other ADCs.
 High precision external components to achieve
required accuracy


Analog
+ Control CLK
I/p
Logic (SAR) STAR
- T
EOC
Comparator
…..
Output
Register
MSB LSB
Binary
….. O/P
DAC

Conversion Process In Successive Approximation ADC
 STEP 1: The MSB is initially set to 1 with the remaining
three bits set as 0. The digital equivalent is compared with
the unknown analog input voltage
 STEP 2: If the analog input voltage is higher than the digital
equivalent, the MSB is retained as 1 and the second MSB is
set to 1. Otherwise the MSB is reset to 0 and the second
MSB is set to 1.
 STEP 3: Comparison is made as given in step 1

to
decide whether to retain or reset the second MSB. The
third MSB is set to 1 and the operation is repeated
down to LSB and by this time, the converted digital
value is available in SAR.


Advantages:
 The conversion time is equal to the “n” clock cycle period for an
n-bit ADC.
 Conversion time is constant and independent of the amplitude
of analog signal

Disadvantages:
 Circuit is complex.
 The conversion time is more as compared to flash type ADC.

Comparison between ADCs
Sr. Successive
No. Parameter Approximation Dual Slope
1 Conversion Time Less More
2 Speed Greater Less
Accuracy of
3 conversion Less Accurate More Accurate
4 Cost More Less
In data acquisition In applications where

5 Applications systems accuracy is required

Specifications of ADC
Resolution:
 Resolution of the ADC is the change in voltage input
necessary for a one bit change in output. It can
also be expressed as percent.

Accuracy:
1
 The accuracy of A/D conversion is limited by the 
2 LSB
due to quantization error and the other errors of the

system. It is the maximum deviation of digital output
from the ideal liner references line. Ideally it
approaches  12 LSB.

Gain and Drift:

 Gain of ADC is the voltage output divided by the voltage
input at the linearity reference line. It can usually be zeroed
out.
 Drift means change in circuit parameters with time. Drift
1
errors of up to  2LSB will cause a maximum errors of one
LSB between the first and the last transition. Very low drift
is quite difficult to achieve and increase cost of the device.
5 ppm/0C is the best commercial value available.

Speed:
 It can be defined in two ways i.e. either the time
necessary to do one conversion or time between
successive conversion at the highest rate possible.
 Speed depends on the setting time of components and
the speed of the logic.


IC ADC
 The ADC0804 is an inexpensive and very popular A/D
converter which is available from a number of different
manufacturers, including National Semiconductor.
 The ADC0804 is an 8 bit CMOS microprocessor compatible
successive approximation A/D converter that is supplied in
a 20 pin DIP.
 It is capable of digitizing an analog input voltage within the
range 0 to +5Vdc, and it only requires a single DC supply
voltage usually - +5Vdc.
 The digital outputs are both TTL and CMOS compatible
IC ADC 0804
Features:
 80C80/8085 Bus compatible- No interfacing Logic is required
 Conversion Time < 100µs
 Easy interface to microprocessors
 Operate in stand alone mode
 Differential Analog Voltage Inputs
 TTL Compatible Inputs and outputs
 On chip clock generator
 Analog voltage Input range – 0V to +5V
 No zero adjust required.
IC ADC 0804
Pin Configuration:

IC ADC 0804
Circuit Diagram:

IC ADC 0804
 In circuit diagram of ADC0804, the controls are wired

such that the converter operates continuously .
 This is also called free running mode.
 The 10KΩ resistor, along with the 150pF

capacitor, establishes the frequency of operation
according to 1
f 
1.1R C
 A momentary activation of the START switch
is necessary.

Memory
 A memory unit is a device to which binary

information is transferred for storage and from
which information is retrieved when needed for
processing.
 A memory unit stores binary information in groups
of bits called words. The internal structure of
memory unit is specified by the number of words it
contains and the number of bits in each word.
Memory
 The memory unit is an essential component in any

digital computer since it is needed for storing
programs and data. Not all accumulated
information is needed by the CPU at the same
time.
 Therefore, it is more economical to use low-cost
storage devices to serve as a backup for storing
the information that is not currently used by CPU
Memory
 Sequential circuits all depend upon

the presence of memory
 A flip-flop can store one bit of information
 A register can store a single “word”

• typically 8, 16, 32 or 64 bits
 Memory stores a large number of words

Organization of Memory
Address Data
 You can think of memory as being one 00000000 0110101100111101
00000001
big array (list) of data
1011111100100100
00000002 1001110011110111
 The address serves as an array index .

.
 Each address refers to one word .
.
of data (e.g., 8-bits, 16-bits, etc.) .
.
 You can read (or modify) the data at any .
.
given memory address, just like you can .
.
read (or modify) the contents of an FFFFFFFD 0000101100001111
array at any given index

1100101000110001
FFFFFFFE 0110101111010000
FFFFFFFF
9/16/2018 Amit Nevase
word 121
Organization of Memory
Memory signals fall into three groups:
 Address Bus - selects one of many memory locations
 Data Bus -
 Read (ROM/RAM): the selected location’s stored data is put
on the data bus
 Write (RAM): The data on the data bus is stored
into the selected location
 Control Bus - specifies what the memory is to do
 Control signals are usually active low
 Most common signals are:
• CS: Chip Select; must be active to do anything
• OE: Output Enable; active to read data
• WR: Write; active to write data
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122
Classification of Memory
Memory
Non Volatile Volatile
ROM RAM
PROM Static
EPROM
EEPROM
Dynamic
FLASH
NOR
NAND
Hard-Disk, CD, DVD, Floppy Disk, Magnetic Tape, USB Flash

9/16/2018 mmA eimt Noevrayes , SD Card 123
Computer Memory Hierarchy
Processor Registers
Very Fast, Very
Small Size Expensive
Small
Capacity Processor Cache
Very Fast, Expensive
Power ON
Medium Size Immediate Term
Medium
Random Access Memory
Capacity Power ON Fast, affordable
Very Short Term
Small Size
Power OFF Flash/USB
Large
Slower, Cheap
Capacity Short
Term
Large Size Power OFF
Very Mid Term Hard Drives
Large Slow, Very Cheap
Capacity
Power OFF
Large Size Long Term
Very
Large CDs, DVD’s and Tape
Capacity Backup
Very Slow, Affordable

Comparison between Volatile & Non-volatile Memory
Volatile Memory Non-volatile Memory

 Information stored is  Information stored is does not
lost if power turns lost if power turns off.
off.  Types - All ROMs,
 Types – All RAMs, EPROM, EEPROM
 SRAM,
Used forDRAM
temporary storage  Used for permanent storage
 Uses mainly Solid state devices  Uses magnetic, optical or sold

state devices
 Fast operation  Slow operation


RAM – Random Access Memory
 RAM stands for Random Access Memory. It is

also
called "direct access memory".
 Random access means that each individual byte
in entire memory can be access directly.
 RAM is used to store data and instructions temporarily.
A program must be loaded into RAM before execution.

 RAM is volatile memory. It means that its contents are

lost when the power is turned off.
 RAM is read/write memory. CPU can read data
from RAM and write data to RAM.
 It is used to store data and instruction while it is being
executed.
 RAM is also called main memory or primary storage.

 RAM plays very important role in the processing speed of a

computer.
 A bigger RAM size provides larger amount of space for
processing. So the processing speed is increased.
 The amount of data that can be stored in RAM is measured
in bytes.
 Most desktop computers typically have 2 GB to 4 GM of
RAM. It also allows the addition of more memory if
needed.
General Block Diagram

Types of RAMs
 Static RAM (SRAM)

 Memory behaves like Latches or Flip-Flops
 Data remains stored as long as power applied
 Dynamic RAM (DRAM)

 Charged or discharged capacitor
 Memory lasts only for a few milliseconds
 Data must be refreshed periodically by
reading and rewriting

Types of RAMs
Typical Microprocessor Memory Configuration

SRAM
 SRAM stands for Static Random Access Memory.
 It can store data without any need of frequent recharging.
 CPU does not need to wait to access data from

SRAM during processing. That is why it is faster than
DRAM.
 It utilizes less power than DRAM. SRAM is more expensive
as compared to DRAM.
 It is normally used to build a very fast memory
known as cache memory.
SRAM
 Static random access memory (SRAM) is a type of volatile

semiconductor memory to store binary logic '1' and '0' bits.
 SRAM uses bi-stable latching circuitry made of

Transistors/MOSFETS to store each bit. Compared to
Dynamic RAM (DRAM), SRAM doesn't have a capacitor to
store the data, hence SRAM works without refreshing.
 In SRAM the data is lost when the memory is not

electrically powered.
SRAM
 SRAM is faster and more reliable than the more common DRAM.
While DRAM supports access times (access time is the time
required to read or write data to/from memory) of about 60
nanoseconds, SRAM can give access times as low as 10
nanoseconds.
 In addition, its cycle time is much shorter than that of DRAM
because it does not need to pause between accesses.
Unfortunately, it is also much more expensive to produce than
DRAM. Due to its high cost, SRAM is often used only as a
memory cache.
SRAM Cell
 The SRAM cell consists of a bi-stable flip-flop connected to
the internal circuitry by two access transistors.
 When the cell is not addressed, the two access
transistors are closed and the data is kept to a stable state,
latched within the flip-flop.
 The flip-flop needs the power supply to keep the
information. The data in an SRAM cell is volatile (i.e., the
data is lost when the power is removed).
 However, the data does not "leak away" like in a DRAM, so
the SRAM does not require a refresh cycle.
SRAM Cell
 Static RAM is fast because the six-transistor configuration
(shown in Fig.) of its flip-flop circuits keeps current flowing in
one direction or the other (0 or 1).
 The 0 or 1 state can be written and read instantly without
waiting for a capacitor to fill up or drain (like in DRAM).
 However, the six transistors take more space than DRAM cells
made of one transistor and one capacitor. When opposite
voltages are applied to the column wires, the flip-flop is
oriented in one of two directions for a 0 or 1.
 At that point, the flip-flop becomes a self-perpetuating storage
cell as long as a constant voltage is applied.
SRAM Cell
A six Transistor CMOS SRAM Cell

SRAM Timing Diagram

Applications of SRAM
 SRAM can be found in the cache memory of a computer or as
part of the RAM digital to analog converter on a video card.
 Static RAM is also used for high-speed registers, caches and
small memory banks like a frame buffer on a display adapter.
 Several scientific and industrial subsystems, modern appliances,
automotive electronics, electronic toys, mobile phones,
synthesizers and digital cameras also use SRAM.
 It is also highly recommended for use in PCs, peripheral
equipment, printers, LCD screens, hard disk buffers, router
buffers and buffers in CDROM / CDRW drives.

DRAM
 DRAM stands for Dynamic Random Access Memory.
 It is used in most of the computers. It is the least expensive
kind of RAM.
 It requires an electric current to maintain its electrical
state. The electrical charge of DRAM decreases with time
that may result in loss of DATA.
 DRAM is recharged or refreshed again and again to
maintain its data.
 The processor cannot access the data of DRAM when it is
being refreshed. That is why it is slow.
DRAM
 DRAM memory technology has MOS technology at the

heart of the design, fabrication and operation.
 The basic dynamic RAM or DRAM memory cell uses a
capacitor to store each bit of data and a transfer device - a
MOSFET - that acts as a switch.
 The level of charge on the memory cell capacitor
determines whether that particular bit is a logical "1" or "0"
- the presence of charge in the capacitor indicates a logic
"1" and the absence of charge indicates a logical "0".
DRAM Cell
 The basic dynamic RAM memory cell has the format

that is shown below. It is very simple and as a result it
can be densely packed on a silicon chip and this makes
it very cheap.
bit line
word line
1-bit DRAM cell

DRAM Cell
 Two lines are connected to each dynamic RAM cell - the Word
Line (W/L) and the Bit Line (B/L) connect as shown so that the
required cell within a matrix can have data read or written to it.
 The basic memory cell shown would be one of many thousands

or millions of such cells in a complete memory chip. Memories
may have capacities of 256 Mbit and more.
 To improve the write or read capabilities and speed, the overall

dynamic RAM memory may be split into sub-arrays.

DRAM Cell
 The presence of multiple sub-arrays shortens the word
and bit lines and this reduces the time to access the
individual cells. For example a 256 Mbit dynamic RAM,
DRAM may be split into 16 smaller 16Mbit arrays.
 The word lines control the gates of the transfer lines,
while the bit bines are connected to the FET channel
and are ultimately connected to the sense amplifiers.

DRAM Array

DRAM Timing
 No clock
 DRAM operations are initiated and completed on both the

rising and falling edges of RAS_L and CAS_L
 The timing for RAS-only refresh cycle is shown on next slide
 This cycle is used to refresh a row of memory without

actually reading or writing any data at the external pins of
the DRAM chip
 The cycle begins when a row address is applied to
the multiplexed address inputs & RAS_L is asserted
DRAM – Refresh Timing
 The DRAM stores the row-address in an internal row-
address register on the falling edge of RAS_L and reads the
selected row of memory array into an on-chip row latch
 When RAS_L is negated the contents of the row are written
back from the row latch

DRAM Refreshing
 Typical devices require each cell to be refreshed once

every 4 to 64 ms.
 During “suspended” operation, notebook
computers use power mainly for DRAM refresh

DRAM Refreshing

DRAM – Read Timing
 Begins like a refresh cycle, selected row is read into the row
latch
 Next a column address is applied to the multiplexed

address inputs & is stored in an on-chip column address
register on the falling edge of CAS_L
 It selects one bit of the just read row which is made

available on the DRAM’s DOUT pin which is enabled as long
as CAS_L is asserted

DRAM – Read Timing

DRAM – Write Timing
 Begins like a refresh or read cycle, WE_L must be

asserted before CAS_L is asserted, this disables DOUT
for the rest of the cycle, even though CAS_L will be
asserted subsequently
 Once the selected row is read into the row latch, WE_L
forces the input bit on DIN to be merged into the row
latch in the bit position selected by the column address

DRAM – Write Timing

Types of DRAM
 Synchronous DRAM (SDRAM)
 Double Data Rate SDRAM (DDR SDRAM)
 Extended Data Out DRAM (EDO DRAM)
 Burst EDO DRAM (BEDO DRAM)
 Rambus DRAM (RDRAM)

Applications of DRAM
 DRAM memories are high volume memories. Some DRAMs

have high speed interfaces such as DDR and DDRII SDRAM,
and some have speed enhancing internal architectures.
 DRAMs with low power internal design techniques are used
in battery operated systems.
 Some DRAM memories are also used for graphics
enhancements like high speed point-to-point interfaces as
well as several internal graphics functions.

Applications of DRAM
 DRAMs can also be used in networking and battery

operated synchronous and asynchronous applications.
 The main memory (the random access memory) in
personal computers is DRAM. DRAM is also the type of
RAM used in workstations and laptop computers as
well as some video game consoles.

Comparison between SRAM & DRAM
SRAM DRAM
 Flip flops using bipolar or MOS  Flip flops using MOS
transistor
transistors are used as
& parasitic capacitance
basic memory cells.
are used.
 Refreshing is not required.
 Refreshing is required
as charge leaks.
 Access time is less
 Access time is more
hence these are faster
hence these are slower
memories.
memories.
 More power consumption.
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 Less power consumption.158
Amit Nevase
 More expensive.
Comparison between SRAM & DRAM
SRAM DRAM
 A SRAM possesses more space in  A DRAM possesses less
space
the chip than DRAM.
in the chip than SRAM.
 Storage Capacity is Less.
 Storage Capacity is More.
 More number of components are
 Less number of
required per cell.
components are required per cell.
 Bits stored in the form of voltage.
 Bits stored in the form
 Applications- Used in cars,
of charge.
household appliances, handheld
 Applications- Used
electronic devices.
computer memory

ROM
 ROM stands for Read Only Memory. The data and instructions in
ROM are stored by the manufacturer at the time of its
manufacturing.
 This data and programs cannot be changed or deleted after
wards. The data or instructions stored in ROM can only be read
but new data or instructions cannot be written into it.
 This is the reason why it is called Read Only Memory. ROM
stores data and instructions permanently. When the power is
turned off, the instructions stored in ROM are not lost. That is
the reason ROM is called non-volatile memory.

ROM
 ROM is used to store frequently used instructions and

data to control the basic input & output operations of
the computer.
 Mostly, frequently used small programs like operating
system routines and data, are stored into the ROM.
When the computer is switched on, instructions in the
ROM are automatically activated. These instructions
help the booting process of computer.
ROM
General Block Diagram

Internal ROM Structure
Typically Implementation
Diode means a
“1” is stored at
this location
data
output
5
active low

Timing Diagram of ROM
 tAA access time from address
access time from chip select
tACS output-enable/disable time
 tOE/tOZ
output-hold time
 tOH

Types of ROM
 Masked ROM
 Programmable ROM (PROM)
 Erasable Programmable ROM (EPROM)
 Electrically Erasable Programmable ROM (EEPROM)

PROM
 PROM stands for Programmable Read Only Memory.

This form of ROM is initially blank.
 The user or manufacturer can write data/program on it
by using special devices. However, once the program or
data is written in PROM chip, it cannot be changed.
 If there is an error in writing instructions or data in
PROM, the error cannot be erased. PROM chip
becomes unusable.

EPROM
 EPROM stands for Erasable Programmable Read Only

Memory. This form of ROM is also initially blank.
 The user or manufacturer can write program or data on it
by using special devices.
 Unlike PROM, the data written in EPROM chip can be
erased by using special devices and ultraviolet rays.
 So program or data written in EPROM chip can be changed
and new data can also be added. When EPROM is in use, its
contents can only be read.
Applications of EPROM
 The most frequent use for an EPROM memory chip is to store
computer BIOS which is used in order to bootstrap the operating
system of a computer.
 EPROMs are also often found in the development of video game
cartridges. Some microcontrollers use an on-chip EPROM in
order to store their program. Examples are some versions of the
Intel 8048 as well as the "C" versions of the PIC microcontroller.
 These microcontrollers were built with a window for debugging
and program development purposes. The same chips are also
developed in opaque OTP packages for production purposes.

EEPROM
 EEPROM stands for Electrically Erasable Programmable

Read Only Memory.
 This kind of ROM can be written or changed with
the help of electrical devices.
 So data stored in this type of ROM chip can be easily
modified.

Applications of EEPROM
 EEPROM memory is used in computers as well as other electronic
devices in order to store small amounts of data which must be saved
when the power is removed such as in calibration tables or device
configuration.
 If larger amounts of static data need to be stored, like in USB flash
drives, a flash EEPROM is more economical to use than a traditional
EEPROM device.
 EEPROM memory can also be found in various other products which
are not strictly memory products, including digital potentiometers,
digital clocks and digital temperature sensors.
 These devices can have a small amount of EEPROM in order to store
calibration information or other data which needs to be available in
case there is a loss of power.
Comparison between RAM & ROM
RAM ROM
 Operations involved- Read  Operations involved- Read.

& Write.
 Temporary Storage.  Permanent Storage.
 Types- SRAM, DRAM  Types- EPROM,
PROM, EEPROM.
 Applications Calculators,  Applications-
- Computers Computers, Microprocessors

Comparison between EPROM & EEPROM
EPROM
 Exposure EEPROM
to ultraviolet light  A voltage of 20V 25V
is
to technique used to erase data. applied to erase
 data.
Selective erasing not  Selective erasing is possible. A
is All get particular locations
possible. can be
erased.
 10 locations
to 15 mins. i.e. Long time  erased.
10ms. i.e. A very short
required for erasing time required for erasing
 Less expensive  More expensive
Comparison between EPROM & EEPROM
EPROM
 It is necessary
EEPROM to remove  It is not necessary to remove
EPROM from circuit for erasing EEPROM from circuit for
data. erasing data.
 Applications- In computer to  Applications- Cell phones,
store operating System Digital cameras etc.

Comparison between EPROM & Flash Memory
EPROM
Flash Memory
 Data can be erased only byte  Data can be erased only block
by byte by giving electrical by block.
pulses.
 Byte programmable.  Block programmable.
 Cost is more.  Cost is less.
 Less speed than flash memory.  More speed than EPROM.
 Life time is greater than flash  Life time is less than

EPROM memory.
memory.
 Memory: RAM and ROM basic building blocks, Read and write

Memory Read Operation
 To read data from the memory, the read cycle is initiated by applying the
address signals. The valid address needs to be maintained stable for a
specified duration tRC the read cycle time.
 Next, the CS and OE signals are activated, after a delay of tGQ, the output
enable access time measured with respect to the High to Low transition of
the OE signal, valid data appears on the data lines.
 The tAQ, address access time is measured from the beginning of the valid
address that appears on the address lines to the appearance of valid data on
the data lines.
 The tEQ measures the chip enable access time which is the time for the valid
data to appear after the High to Low transition of the chip select signal CS.

Memory Read Operation

Memory Write Operation
 To write data from the memory, the write cycle is initiated by applying the
address signals. The valid address needs to be maintained stable for a
specified duration tWC the write cycle time.
 Next, the CS and WE signals are activated. The write enable signal WE is
activated after a minimum time of tS(A) the address setup time which is
measured from the beginning of the valid address.
 The time for which the WE signal remains active is known as the write pulse
width. After the WE signal becomes active the data that is to be written in
the memory at the addressed location is applied at the data lines.
 The WE signal must remain valid after data is applied at the data input lines
and must remain valid for a minimum time duration tWD. The data must
remain valid for a time th(D), hold time after WE signal is deactivated.
Memory Write Operation


Programmable Logic Devices
 PLDs are semiconductor devices can be
that programmed to obtain required logic
 device.
Because of the advantage of re-programmability, they
have replaced special purpose logic devices like Logic
gates, flip-flops, counters and multiplexers in many
semicustom applications.
 It reduces design time and thus reduces time for the
product to reach the market.

 It consists of arrays of AND and OR gates, which can be
programmed to realize required logic function.
 Device programmer blows fuses on the PLD to control
each gate operation.
 Inexpensive software tools are used for quick
development, simulation and testing, therefore design
cost is comparatively low.
 Another important advantage is that customer can
modify their design, based
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on changes in requirement.
Amit Nevase 183
 Programmable Logic Devices (PLDs) are the integrated circuits. They contain
an array of AND gates & another array of OR gates.
 There are three kinds of PLDs based on the type of array(s), which has
programmable feature.
- Programmable Read Only Memory (PROM)
-Programmable Array Logic (PAL)
-Programmable Logic Array (PLA)
-Generic Array Logic (GAL)
 The process of entering the information into these devices is
known
as programming.
 Basically, users can program these devices or ICs electrically in order to
implement the Boolean functions based on the requirement.
9/1sHere, the term programming
6/o20f1t8ware
refers to hardware programming but
Amit Nevase
not 184

Programmable Read Only Memory
(PROM)
 Read Only Memory (ROM) is a memory device,
which stores the binary information permanently.
 That means, we can’t change that stored information
by any means later.
 If the ROM has programmable feature, then it is
called as Programmable ROM (PROM).
 The user has the flexibility to program the
binary information electrically once by using PROM
programmer.
 PROM is a programmable logic device that has fixed AND
array & Programmable OR array.
(PROM)
 Here, the inputs of AND gates are not of programmable type. So, we have to
generate 2n product terms by using 2n AND gates having n inputs each. We can
implement these product terms by using nx2n decoder. So, this decoder
generates ‘n’ min terms.
 Here, the inputs of OR gates are programmable. That means, we can program
any number of required product terms, since all the outputs of AND gates are
applied as inputs to each OR gate. Therefore, the outputs of PROM will be in
the form of sum of min terms.
(PROM)
Example: Let us implement the following Boolean functions using PROM.
A( X ,Y , Z )  m(5, 6, 7)
B( X ,Y , Z )  m(3, 5, 6, 7)

(PROM)
 The given two functions are in sum of min terms form
and each function is having three variables X, Y & Z. So,
we require a 3 to 8 decoder and two programmable OR
gates for producing these two functions.
 Here, 3 to 8 decoder generates eight min terms. The
two programmable OR gates have the access of all
these min terms. But, only the required min terms are
programmed in order to produce the respective
Boolean functions by each OR gate. The symbol ‘X’ is
used for programmable Amit
9/16/2018
connections.
Nevase 189

Programmable Logic Array (PLA)
 PLA is a programmable logic device that has

both
Programmable AND array & Programmable OR
array. Hence, it is the most flexible PLD.

 Here, the inputs of AND gates are programmable. That means each AND gate
has both normal and complemented inputs of variables. So, based on the
requirement, we can program any of those inputs. So, we can generate only
the required product terms by using these AND gates.
 Here, the inputs of OR gates are also programmable. So, we can program any
number of required product terms, since all the outputs of AND gates are
applied as inputs to each OR gate. Therefore, the outputs of PAL will be in the
form of sum of products form.

Example: Let us implement the following Boolean functions using PLA.
A  XY  X Z
B  XY  YZ  X Z

 The given two functions are in sum of products form.
The number of product terms present in the given
Boolean functions A & B are two and three
respectively. One product term, Z′XZ′X is common in
each function.
 So, we require four programmable AND gates & two
programmable OR gates for producing those two
functions.
 The programmable AND gates have the access of both
normal and complemented inputs of variables. In the above
figure, the inputs X , X ,Y ,Y , Z & Z , are available at the

inputs of each AND gate. So, program only the required
literals in order to generate one product term by each AND
gate.
 All these product terms are available at the inputs of each
programmable OR gate. But, only program the required
product terms in order to produce the respective Boolean
ffunctions
o20r18programmable
9/1 6/ by each OR gate. The symbol ‘X’ is used 195
Applications of PLA
 PLA is used to provide control over datapath.
 PLA is used as a counter.
 PLA is used as a decoders.
 PLA is used as a BUS interface in programmed I/O.


Programmable Array Logic
(PAL)
 PAL is a programmable logic that has
device
Programmable AND array & fixed OR array.

 The advantage of PAL is that we can generate only the
required product terms of Boolean function instead of
generating all the min terms by using programmable
AND gates.

(PAL)
 Here, the inputs of AND gates are programmable. That means each AND gate
has both normal and complemented inputs of variables. So, based on the
requirement, we can program any of those inputs. So, we can generate only
the required product terms by using these AND gates.
 Here, the inputs of OR gates are not of programmable type. So, the number
of inputs to each OR gate will be of fixed type. Hence, apply those required
product terms to each OR gate as inputs. Therefore, the outputs of PAL will be
in the form of sum of products form.

(PAL) Let us implement the following Boolean functions using PAL.
Example:
A  XY  X Z
B  XY  Y
Z

(PAL)
 The given two functions are in sum of products form.
There are two product terms present in each Boolean
function. So, we require four programmable AND gates
& two fixed OR gates for producing those two
functions.

(PAL)
 The programmable AND gates have the access of both normal
and complemented inputs of variables. In the above figure, the
inputs X , X ,Y ,Y , Z & , are available at the inputs of each AND
Z
gate. So, program only the required literals in order to generate
one product term by each AND gate. The symbol ‘X’ is used for
programmable connections.
 Here, the inputs of OR gates are of fixed type. So, the necessary
product terms are connected to inputs of each OR gate. So that
the OR gates produce the respective Boolean functions. The
symbol ‘.’ is used for fixed connections.
Advantages of PAL
 Highly efficient
 Low production cost as compared to PLA
 Highly secure
 High Reliability
 Low power required for working.
 More flexible to design.


Generic Array Logic (GAL)
 A GAL or Generic Array Logic device consists of a

re-
programmable PAL matrix and a programmable output-cell.
 GAL is an improved form of PAL which uses electrically erasable
CMOS cells instead of fuses. Therefore, AND matrix of GAL can
be re-programmed several times unlike one time programmable
PAL devices.
 AND matrix is followed by fixed OR matrix (inside output cell),
used to sum off all min termsAmitfrom

9/16/2018 Nevase the AND output. 205
Block Diagram of Generic Array Logic (GAL)

Generic Array Logic (GAL)
 Another added feature of GAL is that it also has reprogrammable
output logic called OLMC (Output Logic Macro-cell).

Output Logic Macro-cell (OLMC)
 As shown in the figure three main components of an output cell are:
- N-input OR,
- D-flip-flop,
- Multiplexers.
 Like in PAL, OR gates are used to sum off min terms from the output of the
AND gates.
 An OLMC cell consists of a D-flip-flop, which is used to implement sequential
circuits.
 Multiplexers in the OLMC cells are used to select the routing of the input
signals to the external output or to the feedback output.
 It is also used to select from the sequential and non-sequential output taken
from the input and output of the D-flip-flop depending on the requirement.

Complex Programmable Logic Devices (CPLD)
 CPLD is defined as the network of PLDs that are

connected
together through a switching matrix.
 The global interconnection matrix, as shown in the figure, is
reconfigurable and so we can change the connections between
the Functional Blocks depending on our requirement.


Logic Block Structure (LB)

 Each Functional Block (FB) in the CPLD contains a re-programmable
AND/OR array along with a bank of macro-cells. Therefore, multiple
types of logic functions, both combinational and sequential circuits,
can be implemented using CPLD.
 As shown in the figure, it is connected to the external world through
the I/O blocks. The entire device contains thousands to tens of
thousands of logic gates. Therefore, more complex designs, other than
PLD devices, can be implemented using CPLD.

Applications of CPLD
 Complex programmable logic devices are ideal for high performance,
critical control applications.
 CPLD can be used in digital designs to perform the functions of boot
loader
 CPLD is used for loading the configuration data of a
field
programmable gate array from non-volatile memory.
 Generally, these are used in small design applications like address
decoding
 CPLDs are frequently used many applications like in cost sensitive,
battery operated portable devices due to its low size and usage of low
power.
References
 Digital Principles by
Malvino Leach
 Modern Digital Electronics
by
R.P. Jain
 Digital Electronics,
Principles and Integrated
Circuits by Anil
K. Maini
9/16/2018
 Digital Techniques by A. Anand
Amit Nevase 215
Online Tutorials
 http://nptel.ac.in/courses/117108038/
38
 https://www.mepits.com/tutorial/80
/vl si/programmable-logic-device-pld
 https://www.tutorialspoint.com/digital
_circuits/digital_circuits_programmable
_logic_devices.htm
 http://ecetutorials.com/digital-
electronics/successive-approximation
- adc-analog-to-digital-converter/


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Rayat Shikshan Sanstha’s

KARMAVEER BHAURAO PATIL

9/16/2018 Amit Nevase 2

 PO 2. Discipline knowledge: Apply Electronics and Telecommunication engineering

 PO 4. Engineering tools: Apply relevant Electronics and Telecommunications

9/16/2018 Amit Nevase 4

 PO 7. Ethics: Apply ethical principles for commitment to professional ethics,

 PO 8. Individual and team work: Function effectively as a leader and team

 PO 9. Communication: Communicate effectively in oral and written form.

 PO 10. Life-long learning: Engage in independent and life-long learning

 PSO 1. Electronics and Telecommunication

 PSO EDA Tools Usage: Use EDA

9/16/2018 Amit Nevase 6

 Use number system and codes for interpreting working

 Use Boolean Expressions to realize the logic circuits.

 Build simple combinational circuits.

 Build simple sequential circuits.

 Test data converters and PLDs in digital

9/16/2018 Amit Nevase 7

L T P C ESE PA Total ESE PA Total

9/16/2018 Amit Nevase 8

9/16/2018 Amit Nevase 9

Distribution of Theory Marks

I Number System and Codes 06 2 2 4 08

II Logic Gates and Logic Families 10 4 4 4 12

III Combinational Logic Circuits 16 4 6 8 18

IV Sequential Logic Circuits 16 4 6 8 18

V Data Converters and PLDs 16 4 4 6 14

 Codes: BCD, Gray Code, Excess-3, ASCII code

 BCD Arithmetic: BCD Addition

9/16/2018 Amit Nevase 12

9/16/2018 Amit Nevase 13

 Encoder/Decoder: Basics of Encoder, decoder, comparison, (IC

9/16/2018 Amit Nevase 14

 Triggering Methods: Edge Trigger & Level Trigger.

 SR Flip Flops: SR Flip Flop, Clocked SR FF with preset & clear,

 JK Flip Flops: Clocked JK FF with preset & clear, Race around

condition in JK FF, Master Slave JK FF, D and T type Flip Flop,

Excitation Tables of Flip Flops, Block schematic and function table

 Shift Register: Logic diagram of 4 bit shift registers - SISO, SIPO,

PIPO, PISO, 4 Bit Universal Shift Registers.

 Counters: Asynchronous Counter: 4 bit Ripple Counter, 4 Bit

Up/Down Counter, Modulus of counter, Synchronous Counter:

Design of 4 bit Synchronous up/down counter. Decade Counter:

Block schematic of IC 7490, IC 7490 as MOD-N Counter, Ring

Counter and Twisted Ring Counter

9/16/2018 Amit Nevase 16

Ladder circuit, DAC IC 0808 specifications, ADC: Block diagram,

types and working of Dual Slope ADC, SAR ADC, ADC IC

operation, types of semiconductor memories.

 CPLD: Basic building blocks and functionality.

9/16/2018 Amit Nevase 18

Ladder circuit, DAC IC 0808 specifications, ADC: Block diagram,

types and working of Dual Slope ADC, SAR ADC, ADC IC

operation, types of semiconductor memories.

 CPLD: Basic building blocks and functionality.

 An analog quantity is one that can take on any value over a

9/16/2018 Amit Nevase 21

 When a physical process is monitored or controlled by

a digital system such as a digital computer, the physical