Chapter 9

Chapter 9
8086/8088 hardware specification
• Both are 40-pin dual in-line packages (DIP)

• 8086 is 16 bit microprocessor with 16-bit data bus.
• 8088 is 16 bit microprocessor with 8-bit data bus.
• 8086 has M/IO pin and 8088 has M/IO pin.
• At pin 34, 8088 has a SSO pin whereas 8086 has BHE/S7 pin.
• Input characteristics of 8086/8088
Logic level Voltage

0 0.8 V maximum
1 2.0 V minimum
• Output characteristics of 8086/8088

Logic level Voltage
0 0.45 V maximum
1 2.4 V minimum
• Noise immunity is the difference between logic 0 output voltage and

logic 0 input voltage level.
• The noise immunity is low and thus it can lead to problem with long
wires or too much load. Thus it is recommended that no more than 10
loads of any type be connected to an output without buffering.
Pin Connections
• AD 7 –AD 0 - right-most 8 bits of memory or I/O Address/data
multiplexed pins.
ALE =1 => Address
ALE =0 => Data
• A15 – A8 – upper half address in 8088.
• AD15 –AD8 – upper half address and data multiplexed in 8086.
• A19/S6 – A16/S3 – multiplexed address and status pins.
• S6 always remain 0.
• S5 indicates the condition of IF flag (interrupt flag)
S4 S3 Functions
0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data Segment
• RD – Whenever this signal is logic 0, it means that the system is
receptive to data from memory or any I/O device.
• READY – If the READY pin is at logic 0, the system goes into wait state
and remains idle.
• INTR – Interrupt request is used to request a hardware interrupt.
• INTR is held high if IF is set, and as a response, 8086/8088 goes into
interrupt acknowledge state.
• TEST – Test pin, is an input that is tested by the WAIT instruction. If
TEST is a logic 0, then WAIT functions as a NOP and if TEST is a logic
1, WAIT waits for test to become logic 0.
• TEST is generally connected to a co-processor.
• NMI – Non-maskable interrupt pin. Is similar to INTR pin, except that
NMI does not check for IF flag as INTR does. If NMI is set, interrupt
vector 2 is used.
• RESET – If this pin is held high for at least 4 clock cycles, then the
system resets itself. While resetting, the IF flag is set to disable all
further interrupts.
• CLK – provides the basic timing signal to the microprocessor.
• Vcc – power supply
• GND – 2 ground pins are there, both must be grounded for proper
operation.
• MN/MX – minimum mode/ maximum mode selection. Maximum mode is
when co-processor exist.
• BHE/ S7 – Bus high enable pin is there in 8086 to select the most
significant data pins(D15-D8) during a read/write operation. S7 is always
logic 1.
• IO/M or M/IO – to indicate the address on the address pins is of memory
or I/O device.
• WR – indicates the system is ready to output data to a memory cell or I/O
device.
• INTA – is response to INTR input pin.
• ALE – Address latch Enable is used to indicate if the AD multiplexed
contain data or address.
• DT/R – data transmit/receive – indicates if the microprocessor is
transmitting or receiving data.
• DEN – activates external data bus buffers.
• HOLD – HOLD input requests a DMA. If the HOLD pin is set, system places
itself in hold state and its data, address and control bus go in high impedance
state.
• HLDA – hold acknowledge – indicates that in response to input HOLD, the
system has gone into hold state.
• SS0 – see table
• LOCK – used to lock peripherals off the system. Each peripheral has to be
locked separately using lock prefix.
• RQ/GT0 and RQ/GT1 – used to request a DMA and grant DMA access. These
are bi-directional pins. (Maximum Mode)
• HOLD and HLDA are used in minimum mode, RQ/GT1 and RQ/GT2 are used in
maximum mode.
QS1 QS2 Function
0 0 Queue is idle
0 1 First byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode

IO/M DT/R SS0 Function
0 0 0 Interrupt ack
0 0 1 Memory read
0 1 0 Memory write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 I/O read
1 1 0 I/O write
1 1 1 Passive
S2 S1 S0 Function
0 0 0 Interrupt Ack
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 passive
Clock Generator – 8284A
• AEN1 and AEN2
RDY1 and RDY2
Address enable 1 and address enable 2 are used together with RDY1
and RDY2 to cause wait states in 8086/8088. These pins together form
the output of the READY pin.
• ASYNC – ready synchronization input adds synchronization to the
READY output.
• READY – This output pin connects to the READY input pin of
8086/8088.
• X1 and X2 – Crystal Oscillator pins connect to an external crystal that is
used as timing input to the clock generator.
• F/C – Frequency/Crystal select. If the pin is held high, an external clock
is provided to the EFI input pin, otherwise internal crystal oscillator is
used.
• CLK – output pin that connects to the CLK input pin of 8086/8088. CLK
is one third of the crystal or EFI input frequency.
• PCLK – peripheral CLK – One sixth of the EFI or crystal clock.
• OSC – same frequency as the crystal or EFI.
• RES – reset input is active when it is low. Resets the clock generator.
• RESET – reset output is connected to RESET input of 8086/8088.
• CSYNC – clock synchronization – is used to provide synchronization
when EFI is used. When internal crystal is used, this pin must be
grounded.
• GND – ground pin.
• Vcc – power supply.
////
Bus Timing
• 8086/8088 use the memory and I/O in periods called bus cycles. Each
bus cycle equals for system-clocking periods (T states)
• During T1, the address of the memory location or I/O is sent out on the
address bus.
• Also, during T1, control signals ALE, DT/R, IO/M or M/IO are also output.
• During T2, 8086/8088 issue the RD or WR signal, DEN, and in case of
write, the data to be written appears on the data bus.
• DEN turns on the data bus buffers, and thus microprocessor accept data
for a read or memory/IO receive data to be written.
• READY is sampled at the end of T2. If READY is low at this time, T3
becomes a wait state (Tw).
• This clock period is provided to access data.
• If this happens to be a read bus cycle, data is sampled at the end of T3.
• In T4, all bus signals are deactivated in preparation for the next bus
cycle.
• This is also the time when microprocessor samples the data bus for data
that is read from memory/IO.
• The trailing edge of WR signal transfers data to memory or IO and
returns to logic 1.
• Memory access time starts when the address appears on the
address bus until data is sampled by the microprocessor on the data
bus in the middle of T3.
• If each clock period is of 200ns, then it means memory access time
is approx 3time periods, i.e. 600ns
• Out of this we need to subtract two things, time for address to be
stable (Tclav) and time for data to be set-up (Tdvcl) on the data bus.
• Usually Tclav is 110ns and Tdvcl is 30ns.
• Thus, memory access time is 600-110-30 = 460ns.
• So, the memory device that is connected to 8086/8088 should take
significantly less time to fetch access data than 460ns.

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Chapter 9

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Chapter 9

8086/8088 hardware specification

• Both are 40-pin dual in-line packages (DIP)

Logic level Voltage

• Output characteristics of 8086/8088

• Noise immunity is the difference between logic 0 output voltage and

QS1 QS2 Function

0 1 First byte of opcode

1 1 Subsequent byte of opcode

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