INTRODUCTION TO ARM 1

ENCODING BRANCH INSTRUCTIONS

(Abbreviated) Format Summary

Instruction Format Cond F I op S Rn Rd Operand2
ADD DP 14 0 0 4 0 reg reg reg
SUB DP 14 0 0 2 0 reg reg reg
ADD (imm) DP 14 0 1 4 0 reg reg imm
LDR DT 14 1 n.a. 24 n.a. reg reg disp
STR DT 14 1 n.a. 25 n.a. reg reg disp

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 Encoding Branch Instructions

• Solution 1: Variable instruction sizes

• Solution 2: Increase number of formats

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 Branch Instruction Format
Cond 10 Target address
4 bits 4 bits 24 bits

Value Meaning Value Meaning

0 EQ (Equal) 8 HI (unsigned Higher)
1 NE (Not Equal) 9 LS (unsigned Lower or Same)
2 HS (unsigned Higher or Same) 10 GE (signed Greater than or Equal)
3 LO (unsigned Lower) 11 LT (signed Less Than)
4 MI (Minus, <0) 12 GT (signed Greater Than)
5 PL (Plus, >=0) 13 LE (signed Less Than or Equal)
6 VS (oVerflow Set, overflow) 14 AL (Always)
7 VC (oVerflow Clear, no 15 NV (reserved)
overflow)
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 Making Decisions

CMP register1, register2

BEQ L1

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 Branch Instruction Format
Cond 10 Target address
4 bits 4 bits 24 bits

Value Meaning Value Meaning

0 EQ (Equal) 8 HI (unsigned Higher)
1 NE (Not Equal) 9 LS (unsigned Lower or Same)
2 HS (unsigned Higher or Same) 10 GE (signed Greater than or Equal)
3 LO (unsigned Lower) 11 LT (signed Less Than)
4 MI (Minus, <0) 12 GT (signed Greater Than)
5 PL (Plus, >=0) 13 LE (signed Less Than or Equal)
6 VS (oVerflow Set, overflow) 14 AL (Always)
7 VC (oVerflow Clear, no 15 NV (reserved)
overflow)
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 Branch Target Encoding

• 24-bits can address 16 MB of address space. This

might seem like enough for many programs.
However today even bigger programs are common.

• Could use:
Program counter = Register + Target address

• What should “Register” be?

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 Branch Target Encoding

• Solution: Use the program counter for “Register”

• Intuition: “if” statements and “loop” bodies

contain must less than 16 MB of instructions.

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 Branch Target Encoding

• Typically PC is incremented before we know

current instruction is a branch. In ARM gets
incremented twice.

• Recall ARM instructions are 4 bytes long.

• ARM requires instructions placed in memory at

an address that is a multiple of 4 bytes.

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 Branch Target Encoding

So, ARM computes:

PCtarget = PCbranch + 8 + 4 x “Target address”

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 Example
Determine encoding for BNE in our earlier while loop
example. Assume the first instruction is at address 0.

Loop: ADD r12,r6, r3, LSL # 2 // r12 = address of save[i]

LDR r0,[r12,#0] // Temp reg r0 = save[i]
CMP r0,r5
BNE Exit // go to Exit if save[i] ≠ k
ADD r3,r3,#1 // i = i + 1
B Loop // go to Loop
Exit:

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 Solution
0x00: Loop: ADD r12,r6, r3, LSL # 2 // r12 = address of save[i]
0x04: LDR r0,[r12,#0] // Temp reg r0 = save[i]
0x08: CMP r0,r5
0x0C: BNE Exit // go to Exit if save[i] ≠
k
0x10: ADD r3,r3,#1 // i = i + 1
0x14: B Loop // go to Loop
0x18: Exit:
PCtarget = PCbranch + 8 + 4 x “Target address”
0x18 = 0x0C + 8 + 4 x “Target address”
0x18 = 0x14 + 4 x “Target address”
0x18 - 0x14 = 4 x “Target address”
0x4 = 4 x “Target address”
“Target address” = 1
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 BNE Exit // go to Exit if save[i] ≠ k

Cond 10 Target address

1 10 1

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 Branch Instruction Format
Cond 10 Target address
4 bits 4 bits 24 bits

Value Meaning Value Meaning

0 EQ (Equal) 8 HI (unsigned Higher)
1 NE (Not Equal) 9 LS (unsigned Lower or Same)
2 HS (unsigned Higher or Same) 10 GE (signed Greater than or Equal)
3 LO (unsigned Lower) 11 LT (signed Less Than)
4 MI (Minus, <0) 12 GT (signed Greater Than)
5 PL (Plus, >=0) 13 LE (signed Less Than or Equal)
6 VS (oVerflow Set, overflow) 14 AL (Always)
7 VC (oVerflow Clear, no 15 NV (reserved)
overflow)
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 BNE Exit // go to Exit if save[i] ≠ k

Cond 10 Target address

1 10 1

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