Second Review 1

VLSI ARCHITECTURE FOR IMAGE
PROCESSING
ALGORITHMS
SECOND REVIEW
MEETING
02.04.2024
Department of Electronics and Communication Engineering
National Institute of Technology Puducherry
Karaikal-609609
GROUP 4
Supervised by: Dr.G.Lakshmi Sutha Nandini Bhardwaj (EC22B1034)
Associate professor Sandya (EC22B1046)
DEPT. of ECE Someshwaran (EC22B1053)
CONTENTS
1. Introduction
2. System Description
3. Implementation on FPGA
4. Block diagram of BBHE
5. Histogram flow chart
6. Generate histogram module
7. Output of histogram module
8. Results
9. Conclusion
10. Future work
INTRODUCTI
ON A field-programmable gate array (FPGA) is an
integrated circuit (IC) that can be programmed or
reprogrammed for the required functionality. They
exhibit parallel processing and fast computation.
This enables FPGAs to be used for a wide range of
digital circuits, from simple logic gates to complex
processors.
FPGAs are often used in prototyping and
development, as they allow engineers to quickly test
and iterate on their designs without having to create
custom ASICs.
SYSTEM DESCRIPTION
The Basys 3 is an entry-level FPGA development
board designed exclusively for the AMD Vivado
Design Suite.
The Basys3 is based on Artix-7.
 It is a starter board of relatively low cost, and has
VGA, USB, along with other ports.
Initial design was done on Model-Sim, and later
migrated to Xilinx’s Vivado Design Suite for more
accurate simulations and timing.
BLOCK DIAGRAM OF BBHE (BRIGHTNESS PRESERVING BI-HISTOGRAM
EQUALISATION )
IMAGE MEAN HISTOGRAM DIVIDE

HISTOGRAM
COMBINE SUB EQUALISE

OUTPUT
IMAGE EACH PIXEL
IMAGE
This block diagram shows how Brightness preserving Bi-histogram equalisation is done.
IMPLEMENTATION ON FPGA
The initial step of designing an architecture is the choosing of suitable
number system. The Floating point number system representation is used
commonly. Even though it provides higher accuracy, computation and system
design are complex. Hence, integer arithmetic was chosen for this work
To implement BBHE on Basys-3 The algorithm was broken down into
logical modules. The first module was identified to be histogram. BBHE was
implemented on RGB image of size 256x256 in MATLAB.
However, due to the complexity of the generated schematic, the initial
design in hardware was made for a binary image with 8 pixels which is
easier to comprehend.
HISTOGRAM FLOW CHART
ImageRA COUNTER
HistRAM M = image INITIALISE
1 =0 values
RESET
0
Intensity values Update the Counter
accessed from Histogram in stops
ImageRAM HistRAM
 Histogram defines the probability density function ) as:
 Where n = total number of pixels in X, = the number of times appears in X, and k = 0; 1; 2;….;L – 1
Notice that n is constant across all values of ).
 The flowchart shows the interaction between different modules for generating histogram
GENERATE HISTOGRAM
MODULE
This module takes image as input and outputs a histogram of frequency of each pixel
value.
This module internally contains counter and 2 ROM one for accessing input data and
other for updating the histogram. Once the module has iterated over all the pixels the done
is set to 1.
The values from the histogram RAM, is read again to verify the values with MATLAB.
SCHEMATIC DIAGRAM
OUTPUT OF HISTOGRAM
MODULE
Image RAM read the values and write to Hist RAM.
OUTPUT OF HISTOGRAM
MODULE
Reading the histogram value from Hist RAM.
RESULTS – UTILIZATION REPORT
(Delay= 3.309ns)
RESULTS – IMPLEMENTATION
IN
Case 1 HARDWARE
: Reset = 1 output =0
Output=0
Reset=1
RESULTS – IMPLEMENTATION
IN
Case 2HARDWARE
: Reset = 0 , output =1
Output=1
Reset=0
CONCLUSION
The design of Histogram on FPGA is matched with the simulation and result form
MATLAB.
Implementation of histogram on Basys – 3 FPGA shows utilization of LUTs - , FFs –
and BRAM - .
The design works with a delay of 9.268ns.
This histogram block can be integrated to other modules to find threshold ,generate
cumulative frequencies for each pixels and create map between input pixel and output
pixel values.
FUTURE WORK:
1. Creating FPGA modules for finding a threshold, generating cumulative
frequencies, and mapping the output.
2. Reduce the power utilization .
3. Compare the FPGA output with MATLAB results.
THANK
YOU

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VLSI ARCHITECTURE FOR IMAGE

IMAGE MEAN HISTOGRAM DIVIDE

COMBINE SUB EQUALISE

 Histogram defines the probability density function ) as:

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