DAY 7- LED,SWITCH,BUZZER,RELAY

INTERFACE WITH FPGA

Quote of the Day
More you work on yourself wider
the Impact will be.
What you will Learn Today
 Led Blinking
 Led –Switch Interface
 Relay Interface
 Buzzer Interface
 About pantechsolutions
● Manufacturers of Lab equipment's(ECE &EEE) and
Sensor Interface
● Manufacturer of Brainsense EEG Headset
● Reconfigurable Algorithms on AI
● Manufacture of AI development Boards
Vision: To help 10 millions students to learn technology
in a easy way
 About me

My Primary Expertise
Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning,
Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising.
Neural Networks : SVM,RBF,BPN
Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman
Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE, Matlab, Open CV

www.pantechsolutions.net https://www.linkedin.com/in/jeevarajan/
 Announcement
● Attendance Link at 8.30 pm
● Minimum attendance required for an E-Certificate is 18
Days. Attendance link will be valid for 2 hrs. after the
event.
● For Internship Candidates no attendance required ,it will
be accessed from the LMS Portal.
(learn.pantechsolutions.net)
● Recorded Video Streaming for some classes to improve
Learning Experience
● Only Xilinx FPGA and tools will be covered.
Spartan 6 FPGA Board

● Xilinx’s Spartan®-6
XC6SLX16-2FTG256C
● MT41J128M16JT-25(DDR3)
● 50MHz Clock
● M25P80 SPI Flash
Board Specifications
● On-Board FPGA: XC6SLX16-2FTG256C;
● On-Board FPGA external crystal frequency: 50MHz;
● XC6SLX16-2FTG256C has rich block RAM resource up to 576Kb
● XC6SLX16-2FTG256C has 14,579 logic cells;
● On-Board M25P80 SPI Flash ， 1M bytes for user configuration code;
● On-Board 256MB Micron DDR3, MT41J128M16JT-125
● On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC
● XC6SLX16 development board has two 64p, 2.54mm pitch headers for extending user IOs.
● All IOs are precisely designed with length matching
● XC6SLX16 development board has 3 user switches
● XC6SLX16 development board has 4 user LEDs;
● XC6SLX16 development board has JTAG interface, by using 6p, 2.54mm pitch header;
● XC6SLX16 development board PCB size is: 6.7cm x 8.4cm;
● Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
JTAG Interface –To Program FPGA
 PIN DETAILS
PIN NO DESCRIPTION PIN NO DESCRIPTION PIN NO DESCRIPTION
1 GND 11 F13 21 K12
2 VCC 12 G14 22 M16
3 GND 13 H16 23 N16
4 E13 14 G11 24 M14
5 B16 15 H14 25 C13
6 C16 16 J16 26 P16
7 D16 17 J12 27 R16
8 E16 18 J13 28 T15
9 F16 19 K16 29 T14
10 F12 20 L14 30 R12
31 GND
32 VCC
Led and Switch Interface
LED INTERFACE

LED 10

LED 11

LED 12

LED 13

LED 14

LED 15

LED 16
LED 9
1

1
D 11 D 12 D 13 D 14 D 15 D 10 D 16 D 17

LED LED LED LED LED LED LED LED

2

2
2
3
4
5
6
7
8
9

R 48
1 5 0 E -S I L
C
1
SWITCH INTERFACE
VC C 3V3

1
10K
R 35
9
8
7
6
5
4
3
2
SW 10
R 37 10k
SW 9 2 1
3
SW 11
R 39 10k
SW 10 2 S W K E1Y -S P S T
3
SW 12
R 40 10k
SW 11 2 S W K E1Y -S P S T
3
SW 13
R 42 10k
SW 12 2 S W K E1Y -S P S T
3
SW 14
R 43 10k
SW 13 2 S W K E1Y -S P S T
3
SW 15
R 44 10k
SW 14 2 S W K E1Y -S P S T
3
SW 16
R 46 10k
SW 15 2 S W K E1Y -S P S T
3
SW 17
R 47 10k
SW 16 2 S W K E1Y -S P S T
3

S W K E Y -S P S T
LED -Switch Code
--Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity Declaration

entity sw_led is
Port ( sw : in STD_LOGIC_VECTOR (1downto 0);
led : out STD_LOGIC_VECTOR (1 downto 0));
end sw_led;
--Architecture Declaration

architecture Behavioral of sw_led is

begin
led <= sw;

end Behavioral;

LED – T9, R9
SWITCH T8,R7
The std_logic Libraries

● std_logic_1164
● std_logic_arith
● std_logic_unsigned
● std_logic_signed
std_logic_1164
● The std_ulogic type
● The std_logic type
● The std_ulogic_vector type
● The std_logic_vector type
● The to_bit function
● The to_stdulogic function
● The to_bitvector function
● The to_stdlogicvector function
● The rising_edge function
● The falling_edge function
● The is_x function
std_logic_arith
● The unsigned type
● The signed type
● The arithmetic functions: +, -, *
● The comparison functions: <, <=, >, >=, =, /=
● The shift functions: shl, shr
● The conv_integer function
● The conv_unsigned function
● The conv_signed function
● The conv_std_logic_vector function
Led Blinking code for one second On & Off
--Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Entity Declaration
entity relay is
port ( clock : in std_logic;
a : out std_logic ● T=1/50 mhz = 20 nano seconds
); ● 1seconds = 1 e9(ns) =1000 000 000 /20 =50000000 (1 Second)
end relay;
--Architecture Declaration
architecture Behavioral of relay is
begin
process(clock)
--Variable Declaration
variable i : integer := 0;
begin
if clock'event and clock = '1' then
if i <= 50000000 then
i := i + 1;
a <= '1';
elsif i > 50000000 and i < 100000000 then
i := i + 1;
a <= '0';
elsif i = 100000000 then
i := 0;
end if;
end if;
end process;
end Behavioral;
RELAY INTERFACE
JP1
1 R LY _N O
1 2 R LY _C VC C 5V0 LS1
2 3 R LY _N C 8
3 5 R LY _N O
R LY _C 3
H EAD ER 3 R 50 330E 4 R LY _N C
1 6
2 7
1

D 19 D 20
D IO D E R ELAY SPD T
LED
2

Q2
BC 847
R 52 1 k 3
R ELAY 1 SOT-23
2
Relay -Switch Code
--Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity Declaration

entity sw_led is
Port ( sw : in STD_LOGIC_VECTOR (7 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0));
end sw_led;
--Architecture Declaration

architecture Behavioral of sw_led is

begin
led <= sw;

end Behavioral;
BUZZER INTERFACE

BUZZER
BUZZER SMALL
VC C 3V3
CON3 LS2
J7
Q1 1
BC 847
2
1
2
3

R 51 1 k
3
1 SOT-23
BU Z Z ER
2
Buzzer -Switch Code
--Library Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity Declaration

entity sw_led is
Port ( sw : in STD_LOGIC_VECTOR (7 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0));
end sw_led;
--Architecture Declaration

architecture Behavioral of sw_led is

begin
led <= sw;

end Behavioral;
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