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To create a program that will execute on the Z80 MPU, we need to know several things. 1. The Programming Model which includes The Instruction Set , Register Set and the Addressing Modes . 2. The System Memory Map :- This gives information regarding the address locations and sizes of the Memory (RAM & ROM) and the I/O devices
Microprocessor Systems I 1
ROM: contains program, constants, lookup tables RAM: contains variables and data structures I/O : Input Output device/s location/s
Microprocessor Systems I
3. The Development Tools to allow the creation of a machine readable program 4. Finally, the problem , a description program that we want to implement. Once we have an idea of what we are trying achieve, then we can design a program to this.
Microprocessor Systems I
In the previous lectures we have introduced the basic concepts of how a general MPU operates. These next lectures will specifically with the Z80 MPU. The lectures will introduce the following 1. INSTRUCTION SET and ADDRESSING MODES 2. INTRODUCTION TO ASSEMBLY LANGUAGE
Microprocessor Systems I
Refresher
MPU instructions are represented by binary words. Each instruction has an unique binary pattern. MPU executes program one instruction at a time. ( FETCH DECODE EXECUTE )
Microprocessor Systems I
Microprocessor Systems I
MPU Instruction Set: The MPU is only capable of performing a limited number of instructions , this is its instruction set. Zilog Z80 MPU can execute 158 different instructions types. The types of instructions a MPU can perform may be generally classified as follows
Microprocessor Systems I
Instruction
Assembler Format
LD A, ( 1825H)
Operand(s) 1825
Microprocessor Systems I
1. 2. 3. 4. 5. 6.
Data Transfer Operations Arithmetic Operations Logical Operations Program Flow Control Input - Output Miscellaneous
Microprocessor Systems I
Data Transfer
Arithmetic Operations
ADD A,5 SUB 5 add constant 5 to Accumulator subtract 5 from the Accumulator
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Logical Operations
OR 0FH bitwise OR of Acc with constant 0FH AND 0FH bitwise AND of Acc with constant 0FH Program Flow Control JP Z,0200H JP NZ,0200H JP C,0200H JP NC,0200H DJNZ 0200H ;THIS OPCODE USES REGISTER B
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Z80 Instruction Set Uses the following Categories to group its operations
Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output Basic CPU Control
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Addressing Modes
Most Z80 Instructions operate on Data stored in
1. Internal Registers ( A,F,B,C,D,E,H,L,SP, e.t.c.) 2. External Memory 3. In I/O Ports For all these Data movement operations, the instruction ( the op-code + operands) must contain information relating to
1. Source of Data (Is it Register,Memory or I/O ?) 2. Destination of Data (Register,Memory or I/O ?)
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Instructing the MPU as to the Data source and the Data Destination is called the ADDRESSING MODE. MPU generally have a variety of ADDRESSING modes The Z80 supports 10. The Instruction Format is as follows
SPECIFIES OPERATION
Microprocessor Systems I
The Z80 Instruction Set Contains Operations described with the following 3 instruction formats 1. Single Byte Op-code Only 2. Two Bytes Op-code + 1 Operand 3. Three Bytes Op-code + 2 Operands
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Reading Mnemonic
LD
HL
DE
OPERAND2 (Reg, Mem , I/O ) (Reg , Mem , I/O )
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Z80 Addressing Modes Ref. Microprocessor Systems Chapter 3 Pg. 63 - 69 1. Register Addressing (Implied, Implicit) Instruction execution involves only contents of registers for source and destination. No memory address need be generated LD A,B LD BC,DE ADD A,C SINGLE BYTE INSTRUCTION FORMAT
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2. Immediate Addressing
In this mode the data required by the instruction is available immediately the full instruction has been read. 2 BYTE and 3 BYTE INSTRUCTION FORMAT
OPCODE followed by DATA Byte(s). Data is often called LITERAL,(meaning a quantity itself)
LD ADD LD OR B,34H A,0EAH BC,1850H 02H 2 BYTE FORMAT OPCODE + OPERAND 3 BYTE FORMAT OPCODE+OPR1+OPR2
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4.Indirect Addressing In this case the instruction does not give the address directly but instead the location of the address. This location may be another memory location or a register.
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5. Index Addressing Using Index Register + an Offset to Specify data Index registers IX and IY (16 bit registers) LD A,(IX + 0) ; address formed from IX contents + 0h 6. Relative Addressing In this mode , the byte following the instruction op-code specifies a 2s complement displacement value. The 2s complement value is added to the PC to enable forwards and backwards jumps in the program.
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1850 1852
JR RST
NZ,0FBH 38H 1111 1011 0000 0100 1s complement 0000 0101 2s complement 5 DECIMAL FB = -5 DECIMAL
0FBH means
IF when executing the jr instruction the Z is still set the PC counter will be altered to jump back five places to location 184DH NB. The PC will be pointing the next instruction location 1852H , therefore 1852H - 5H = 184DH
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Why do we need different Addressing Modes ? Read Discussion on Page 70. Register Addressing Reduces external Bus access.
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org $0 jp start
start
loop
Microprocessor Systems I
AS80 Assembler for i8080 [1.31]. Page 1 --------------------------------- FIRST.ASM --------------------------------12 lines read, no errors in pass 1. 0000 = org $0 0000 : c30018 jp start
1800 = 1800 : 215018 1803 : 0620 1805 : af 1806 : 77 1807 : 23 1808 : 05 1809 : 20fb 180b : ff No errors in pass 2.
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