Amplifier
Amplifier
Amplifier
Amplifiers
Ideal OP Amps Basic OP Amp Circuit Blocks Analog Computation Nonlinear OP Amp Applications OP Amp Considerations Guarding Passive Filters Active Filters VCO(Voltage Controlled Oscillator)
Function of Amplifiers
Amplifiers provides
GAIN Filtering,
Sensor
Digital Computer
Chap 0
Ideal OP Amps
Amp TF (Gain):
Av !
vo vi
Av u 1 OP Amp is preferred
Usually
Chap 0
Assumptions
Open
loop Gain = Infinity Input Impedance Rd = Infinity Output Impedance Ro = 0 Bandwidth = Infinity
Infinite Frequency Response
vo=0
when v1 = v2
No Offset Voltage
Chap 0
Note
v0 = A(v2 v1)
If v0 = g, A = g (Typically 100,000)
Then v2 v1 = 0 v2 = v1
Since v2 = v1 and Rd = g
We can neglect the current in Rd
Rule 1
When the OP Amp is in linear range the two inputs are at the same voltage No Current flows into either terminal of the OP Amp
Rule 2
Chap 0
Inverting Amplifier Noninverting Amplifier Unity-Gain Amplifier Differential Amplifier Instrumental Amplifier The Electrocardiogram Amplifier
Chap 0
Inverting Amplifier
From Rule 1
v-
= v+ = 0
ii = vi / Ri , , if = vo / Rf
vi
/ Ri = - vo / Rf
vo / vi = -Rf / Ri
Virtual Ground
-Rf / Ri
7
Chap 0
Linear Range
Input Impedance
Low (Ri) Increasing Ri Decreasing Gain
Saturation
Chap 0 8
Concept of Loading
: Sensor
Vx Vy = Vx Vx v Rx / (RL + Rx)
Digital
Let RL >> Rx
Vy = Vx Amp
Rx x Vx Vy RL
Chap 0
Noninverting Amplifiers
Noninverting Amp
By Rule 2
Vo = If v (Rf + Ri) Vi = If v Ri Vo = Vi v (Rf + Ri)/Ri
By Rule 1 Vi
Chap 0
10
UnityUnity-Gain Amplifier
Homework #2-1
Vo = Vi Applications
Buffer amplifier
Isolate one circuit from the loading effects of a following stage
Impedance converter
Data conversion System (ADC or DAC) where constant impedance or high impedance is required
Chap 0
11
Differential Amplifiers
Combination of Inverting and Noninverting Amp Can reject 60Hz interference Electrocardiogram amplifier
Chap 0
Differential Instrumentation
Noninverting
12
By Rule 2
V5 = I2 * R2 V2 = I2 * R1 + V5 = V5 * R1 /R2 + V5 V5 = R2 * V2 / (R1 + R2)
By Rule 1
V1 = R1 * I1 + V5 V5 = R2 * I1 + V6 V6 = (V2 V1) * R2 / R1
Chap 0
13
If V1 = V2, then V6 = 0
The Higher CMRR, the better quality Typically, 100 ~ 10,000 60Hz noise common to V1 and V2 can be rejected
Chap 0 14
Instrumentation Amplifiers
Instrumentation Amplifier
Differential
Amp with High Input Impedance and Low Output Impedance Two Noninvering Amp + One Differential Amp
Chap 0
15
Homework #2-2
Show
that
= DG / CMG = DG
Overall CMG = 0
High
CMRR
Chap 0
Analog Computation
Chap 0
18
Inverter
Rf / Ri = 1
Application
Chap 0
19
Adder
Chap 0
20
Integrator
Homework #2-3
Drawbacks
Chap 0
21
Practical Integrator
Reset
S1
Closed, S0 Open
Inverter C is initialized to Vr
Integrate
S1
Open, S0 Closed
Hold
S1
Chap 0
Differentiators
Homework #2-4
Drawbacks
Practical Differentiator
Ri !
Chap 0
23
Comparators
Drawbacks
Vi > Vr
Vo = -Vs
If Vi = Vr + small noise
Rapid fluctuation between s Vs
Vi < Vr
Vo = Vs
Chap 0
24
Positive Feedback
Hysteresis loop Can remove the effect of Small Noise
Homework #2-5
Show that
Reduce Fluctuation
Chap 0
25
Rectifiers
Chap 0
26
OP Amp Considerations
Compensation
Undesirable Oscillation at High frequency
Add external Capacitance according to Spec sheet
To minimize errors
feedback R should be low (<10K;)
Slew Rate
Maximal rate of change of amplifier output voltage
Ex: Slew rate of 741 = 0.5 V / Qs Time to output change from 5V to 5V = 20 Qs
Chap 0
28
Power Supply
Usually s15V
Linear Range s13V
Different OP Amps
Bipolar Op Amps
Good input offset stability Moderate input bias current and Input resistances
FET
Very Low input bias current and Very High Input resistances Poor Input offset voltage stability
Chap 0
29
Prices
Chap 0
30
Guarding
Elimination of Surface Leakage Currents Elimination of Common Mode Signals Very important in practice
But
Chap 0
31
Passive Filters
Passive Circuits
Contains
Filters
Eliminate
unwanted signal from the loop Low Pass, High Pass, Band Pass, Notch,
Chap 0 32
Homework #2-6
Show that
Vo 1 ! , X ! RC Vi 1 j[X
Number of C and L
Chap 0
33
Pass desired High frequency signal and reject undesired low frequency signal
Homework #2-7
Show that
Vo j[X ! , X ! RC Vi 1 j[X
Chap 0
34
Homework #2-8
Show that
Vo 1 ! Vi ( j[ / [ c ) 2 (2^ j[ / [ c ) 1 [c ! 1 R C ,^ ! 2 L LC
Number of C and L
Chap 0
35
Homework #2-9
Show that
Vo [2 ! Vi ( j[ / [ c ) 2 (2^ j[ / [ c ) 1 [c ! 1 R C ,^ ! LC 2 L
Number of C and L
^ !1 ^ "1
Chap 0
36
Identical frequency response with Passive filter Very Low Output impedance
Chap 0
37
Identical frequency response with Passive filter Very Low Output impedance
Chap 0
38
Chap 0
39
Butterworth Filters
Maximally Flat Magnitude response in pass band High Attenuation Rate
Chebyshev Filters
Maximum Attenuation Rate Ripple in pass band
Bessel Filters
Maximally flat time delay in response to step input Attenuation Rate is very gradual
Chap 0
40
C when [0 = R0 = 1
Chap 0
41
Low pass five-pole Butterworth filter with a corner frequency of 200Hz and input resistance of 50K;
Economic Solution = 3rd order + 2nd order Desired R and C ?
C1A = ([0 R0 C0 ) / ([ R) = 1x1x1.753 / 2Tx200x50K = 27.9 nF C2A = 21.6 nF, C3A = 6.7 nF, C1B = 51.5 nF, C2B = 4.9 nF
Chap 0
42
VCO converts an input voltage to a series of output digital pulses whose frequency is proportional to the input voltage Applications
ADC Digital Transmission Telemetry Digital Voltmeter
Chap 0
43
VCO (Cont.)
Module form
Monolithic IC form
Less expensive, Small size Lower drift, Better flexibility of frequency range
Examples
LM331
Low cost VCO from National Semiconductor Maximum nonlinearity 0.01% over 1 ~ 100KHz
CD4046B
PLL contains VCO Maximum nonlinearity 1.0% over 1 ~ 400MHz
Chap 0
44
Control loop
Goal
Minimize z(t) s(t) = r(t)
Homework #2-10
PLL
Chap 0
45
VCO Interfacing
Output of VCO
# of pulse / Duration
Duration
Controlled by Sampling Gate
# of Pulse
Counted in Counter
Chap 0
46
Divider Circuit
Output Voltage
R1, R2
Chap 0
48
Vo
Sensor
0
Insulation
49
R1, R2
Chap 0
Vo = 5 {12 / (10+12)} = 2.73V Minimum Vo = 5 { 4 / (10 + 4)} = 1.43V Maximum Z = (10K || 12K) = 120/22 K; Minimum Z = (10K || 4K) = 40/14 K; Maximum Power = (Vo)2/R2 = (2.73)2/12K = 0.62mW Minimum Power = (1.43)2/4K = 0.51mW
Chap 0
50
Bridge Circuit
Eo = Ea Eb Ea = {R3/(R1 + R3)} E Eb = {R4/(R2 + R4)} E Eo = {(R2R3 R1R4) / (R1+R3)(R2+R4) } E Null Condition (Eo = 0) R1R4 = R2R3 E Example (R1 is sensor) Eo : q
Null Condition R2
Chap 0
51
Thevenins Equivalent R1 E a R3 a IG b RG G R2
b R4
RTH = R1 || R3 + R2 || R4 = R1R3/(R1+R3) + R2R4/(R2+R4) VTH = {(R2R3-R1R4) / (R1+R3)(R2+R4)} E = Eo IG = VTH / (RTH +RG) Example
R1=R2=R3=2K;,
RTH VTH
Chap 0
52
Bridge Sensitivity
R E R G R+(R R E R G R+(R R+(R R E R+(R R+(R G R+(R R+(R
Output (Approximation)
Eo = ((R/4R)E Eo = ((R/2R)E Eo/(R = E/2R Eo = ((R/R)E Eo/(R = E/R
Sensitivity
Eo/(R = E/4R
More Sensitive
Accuracy of Approximation
(R < 0.05R, then 98% Accurate (R < 0.1R, then 95% Accurate
53
Chap 0
Bridge Resolution
Detector Example
Resolution
R1=R2=R3=R4=120;,
Chap 0
54
Lead Compensation
R E R G
R RL R RL E
R G R
R RL R RL
55
Chap 0
R1 E a R3 Ex
R2
G b R4
Ex = {R4/(R2+R4)}E - {R3/(R1+R3)}E
Chap 0
56
AC Bridges
Example
Z1 = 1K; Z2 = 2K; Z3 = R(1K;) + C(1QF) Z4 = R4 (?) + C4(?)
Z1Z3 = Z2Z4
Z1 E a Z3 G
Z2 b Z4
Chap 0
Summary of Bridge
Convert variation of resistance to variation of voltage Nonlinear response to a linear variation of resistance
Assumed
Chap 0
58
Desired Response
Step Response
Model
Zero order First order Second order
Real Application
Assumed Zero Order or First Order Model or Table is used
Chap 0
59
b(t) = Kvc(t-td) + bd
td = bd = 0
b(t) = K v c(t) Ideal with Gain K
td = 0
b(t) = K v c(t) + bd Biased
bd = 0
b(t) = K v c(t-td) Time Delayed
t
60
Chap 0
b(t ) ! bi (b f bi )[1 e t / X ]
b(t ) bi ! (b f bi )[1 e t / X ]
t=X
b(t ) bi ! [1 e1 ](b f bi ) ! 0.6321(b f bi )
63%
t = 5X
b(t ) bi ! 0.993(b f bi )
61
X
Transient
Chap 0
Steady State
Temperature sensor
Linear
TF: 33mV/rC, with X=1.5sec Find output at 0.75sec after input 20 41rC
From
b(t ) ! bi (b f bi )[1 e t / X ] b(0) ! bi = 20rC x 33mv/rC = 660mV b(g) ! b f = 20rC x 33mv/rC = 1353mV b(t ) ! 660 (1353 660)[1 e t /1.5 ]
mV
b(0.74) = 932.7 mV
932.7 mV / 33 mV / rC = 28.3rC
R (t ) w R0 e at sin(2T f n t )
Chap 0
63