LECTURE NOTES

ON

EC 203
DIGITAL SYSTEM DESIGN

Adder/Substractor

Dr. RUPESH KUMAR SINHA

DEPARTMENT OF ELECTRONICS AND
COMMUNICATION
BIT, MESRA,RANCHI
Ph No. 9470369133
E-Mail: rk.sinha@bitmesra.ac.in
 Combinational Circuit
There are two general categories of Digital Circuits
(i). combinational circuit
(ii) sequential circuit
– In a combinational circuit, the input values explicitly
determine the output
– In a sequential circuit, the output is a function of the input
values as well as the existing state of the circuit
• As with gates, we can describe the operations
of entire circuits using three notations
– truth tables
– Boolean expressions
– logic diagrams
 BINARY ADDER
 The circuits used to perform arithmetic operations are constructed using
combinatorial logic.
 Digital system can perform various operation over binary data
 The most basic and most commonly used arithmetic operation is the addition
of two binary digits.
 This simple addition consists of four possible elementary operations:
• 0 + 0 = 0;
• 0 + 1 = 1;
• 1 + 0 = 1;
• And 1 + 1 = 10 (that is binary 22).
• The first three operations produce a sum of one digit,
• but last operation, when both augend and addend bits are equal to 1,
then the binary sum consists of two digits.
 The higher significant bit of this result is called a ‘Carry’ or C.
 Whereas least significant bit in all case is called ‘SUM’ or S
BINARY Addition
 BINARY ADDER
 An ‘ADDER’ is a combinational circuit that performs simple binary addition.
 To perform complete one bit binary addition ( See column 5 & 6 at HSB in pre.example)
An ‘ADDER’ requires
• Three inputs, (two for augend and addend & one for carry) and
• Two outputs, (for sum and carry),.
Adder, which performs complete one bit binary addition is known as ‘Full Adder’

 But, An partial one bit binary addition can be performed by ignoring carry bit.
This partial one bit addition (See column 1, 2, 3 & 4 at LSB in example)
• Two inputs, two for augend and addend and
• Two outputs, for sum and carry,.

Adder, which performs partial one bit ‘partial’ binary addition is known as ‘Half Adder’
 Design of Binary ADDER: Half Adder
 An Half adder performs partial one bit binary addition for two input bit
 It must have two inputs (augend and addend) and two outputs (sum and carry).
 This circuit called ‘Half Adder’ as it can performs only partial addition
operation not complete one bit addition, as it ignores ‘input carry’.
 The K map for S (SUM) and C (Carry) and resulting expression A B and A.B
 Half Adder
 If A and B are binary inputs to the half adder, then
• the logic function to calculate sum S is Ex -OR of A and B and
• logic function to calculate carry C is AND of A and B.
 Combining these two, the logical circuit to implement the combinational circuit of
Half Adder is shown below.
 Half Adder using NAND Gates
 As we know that NAND and NOR are called universal gates as any logic system
can be implemented using these two
 The half adder circuit can also be implemented using them.
 We know the NAND only circuit of Ex-OR gate and AND gate. Same is used her.e
 Figure shows the Half Adder circuit using NAND gates only.
 Five NAND gates are required in order to design a half adder. The circuit to realize
half adder using NAND gates is shown below.
 Half Adder using only NOR Gates

Limitations of Half Adder

 The reason these simple binary adders are called Half Adders is that there is no
scope for them to add the carry bit from previous bit.
 This is a major limitation of half adders when used as binary adders especially in
real time scenarios which involves addition of multiple bits.
 To overcome this limitation, full adders are developed
 Full Adder
 Full adder is a digital circuit used to perform complete one bit binary addition
 It is used to calculate the binary sum of three input binary bits, which is the
main difference between this and half adder.
 Full adders are complex and difficult to implement when compared to half adders.
 Two of the three bits are same as before: A the augend bit and B the addend bit
 The additional third bit is carry bit from the previous stage and is called Carry,

in generally represented by CIN.

 It calculates the sum of three bits along with the carry.
 The output carry is called Carry – out and is represented by COUT.
 Design of Binary ADDER: Full Adder
K – Map for Sum S
The truth table for full adder

Expression for Sum, S

S = A’B’C+A’BC’+AB’C’+ABC
K – Map For Carry – out COUT

Expression for COUT

COUT = AB + ACIN + BCIN
 Full Adder Circuit
 In order to implement a combinational circuit for Full Adder, it is clear
from the equations that we need
 For Sum  For Carry-out.
 4 three input AND gates and  3 two input AND gates and
 1 four input OR gate and  1 three input OR gate
 The logic circuit for full adder is shown below.
 Design of Binary ADDER: Full Adder
We know the equations for S and COUT from earlier
K – Map for Sum S
calculations as
S = A’B’Cin+A’BC’in+AB’C’in+ABCin

Cout = AB + ACIN + BCIN

We can rewrite the equation for sum as follows.

S = A’B’Cin+A’BC’in+AB’C’in+ABCin

= Cin(A’B’ + AB) + C’in (A’B + AB’ )

 Expression for Sum, S
 B) + C’in (A B )
= Cin(A  S = A’B’Cin +A’BC’in+AB’ C’in+ABCin
= Cin (A + C’
B)’ in (A B) K – Map For Carry – out COUT
Therefore S = CIN (A B)

Cout is simplified as

COUT = A B + ACIN + BCIN.

= A B + ACIN + ABCIN + A’BCIN (as A’+A =1)

= A B + ABCIN + ACIN + A’BCIN

= A B + ACIN + A’BCIN (as 1+CIN = 1)

= A B + ACIN (B+B’) + A’BCIN (as B+B’ =1) Expression for COUT

COUT = AB + ACIN + BCIN
= A B + ABCIN 
+ AB’CIN + A’BCIN
Implementation of Full Adder using Two Half Adder
and one OR Gate
 Implementation of Full Adder using Two Half Adders

 A full adder can be formed by logically connecting two half adders.

 the full adder is simply two half adders joined by an OR Gate.
 The block diagram shows the implementation of a full adder using two half adders.
 The first half adder will be used to add A and B to produce a partial Sum.
 The second half adder logic can be used to add CIN to the Sum produced by
the first half adder to get the final S output.
 If any of the half adder logic produces a carry, there will be an output carry.
 Thus, COUT will be OR function of the half-adder Carry outputs (of Both HA).
 N-Bit Parallel Adder
 The Full Adder is capable of adding only two single digit binary number
along with a carry input.
 But in practical we need to add binary numbers which are much longer than
just one bit.
 To add two n-bit binary numbers we need to use the n-bit parallel adder.
 It uses ‘n’ number of full adders in cascade.
 The carry output of the previous full adder is connected to carry input
of the next full adder.
 If all input bits of the two numbers (A & B) are applied simultaneously in
parallel, the adder is termed a ‘Parallel Adder’.
 Ripple-Carry Adder
 It is possible to create a logical circuit using multiple full adders to add N-
bit numbers.
 Each full adder inputs a Cin, which is the Cout of the previous adder.
 This kind of adder is called a ‘ripple-carry adder’, since each carry bit
"ripples" to the next full adder.
 Note that the first (and only the first) full adder may be replaced by a half
adder (under the assumption that Cin = 0).
Propagation Delay
 Propagation Delay
 This propagation delay is a limiting factor on the adder speed.

 The signal from the input carry to the output carry propagates through an AND
gate and OR gate, which constitute two gate levels.
 If there are four full adder stages, the output carry would have 2 x 4 = 8

levels from C0 to C4.

 The total propagation time in this 4-bit adder would be the propagation
time in one half adder (which is the first half adder) plus eight gate levels.
 Assuming that all the different types
of gates have same propagation
delay, say T, the propagation delay
of adder can be generalized as (2n +
1) T, where n is the number of
stages. In this example, n = 4, so
the Total Delay is (2 x 4 + 1) T = 9T
 Propagation Delay
Ripple Carry Adders

Total Delay is (2 x 4 + 1) T = 9T
 Gate Delay in Ripple-Carry Adder
 Ripple carry Adder are slow. There is a very long path from A0, B0, Cin to
Cout and S3
 In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path
(worst case) delay is 1 (from input to carry in first adder) + 31 * 2 (for
carry propagation in later adders) = 63 gate delays
 For an n bit ripple adder, the longest path has 2n+1 gates
To Reduce Delay Ripple-Carry Adder
 Carry-look-ahead adder
 Since all other arithmetic operations are implemented by successive
additions, the time consumed during addition process is very critical.
 For fast applications, a better design is required. The carry-look-ahead
adder solves this problem by calculating the carry signals in advance,
based on the input signals.
Method for Fast Carry Generation
Method to compute Fast Carry Generation
Method to compute Fast Carry Generation
Logic Circuit for Fast Carry Generation
Method to compute Fast Carry Generation
Logic Circuit for Carry-Look-Ahead Adder
 Serial binary adder
 The serial binary adder or bit-serial adder is a digital circuit that
performs binary addition bit by bit.
 The serial full adder has three single-bit inputs for the numbers to be added
and the carry in. There are two single-bit outputs for the sum and carry out.
 The carry-in signal is the previously calculated carry-out signal. The
addition is performed by adding each bit, lowest to highest, one per clock
cycle.
 Serial binary addition is done by a flip-flop and a full adder.

 The flip-flop takes the carry-out signal on each clock cycle and provides its
value as the carry-in signal on the next clock cycle.
 After all of the bits of the input operands have arrived, all of the bits of the
sum have come out of the sum output.
Serial adder
 Difference between serial and parallel adder
Serial adder:
1) Slower
2) It uses shift registers
3) It requires one full adder circuit.
4) It is sequential circuit.
5) Time required for addition depends on number of bits.

Parallel adder:
1) Faster
2) It uses registers with parallel load capacity
3) Number of full adder circuit is equal to no. of bits in binary
adder.
4)It is a combinational circuit
5)Time required does not depend on the number of bits
 Half Subtractor
 The half subtractor is a combinational circuit which is used to perform
subtraction of two bits.
 It has two inputs, the minuend Ai and subtrahend Bi and two outputs the

difference D and borrow out Cout .

 The borrow out signal is set when the subtractor needs to borrow from the
next digit in a multi-digit subtraction.
 That is, Barrow bit Cout is 1 when Ai <Bi . Since Ai and Bi are bits, Cout = 1

if and only if Ai =0 and Bi=1.

 An important point worth mentioning is that the half subtractor diagram aside

implements Ai – Bi and not Bi – Ai since Cout on the diagram is given by

Cout = A’i Bi
 This is an important distinction to make since subtraction itself is not

commutative, but the difference bit D is calculated using an XOR gate which
is commutative.
 Half Subtractor

Ai Bi D C1
0 0 0 0 A’B’ D =(Ai  Bi)
0 1 1 1 A’B
1 0 1 0 A B’
1 1 0 0 A B
C1=(A’i Bi)

A D D =(Ai  Bi)
B

C1
C1=(A’i Bi)
 Full Subtractor
 The full subtractor is a combinational circuit which is used to perform subtraction of

three input bits: the minuend Ai, subtrahend Bi, and borrow in Cin .
 The full subtractor generates two output bits: the difference D and borrow out Cout.

 Cin is set when the previous digit borrowed from Ai .

 Thus, Cin is also subtracted from Ai as well as the subtrahend Bi .

 Or in symbols: Ai – Bi – Cin
 Like the half subtractor, the full subtractor generates a borrow out when it needs to
borrow from the next digit.
 Since we are subtracting Bi and Cin by Ai, a borrow out needs to be generated

when Ai < Bi +Cin.

 When a borrow out is generated, 2 is added in the current digit. (This is similar to
the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we
borrow.).
 Therefore, D = Ai – Bi – Cin + 2 Cout
Full Subtractor
Half Subtractor Using Nand only Gate
 Full Subtractor using Two Half Adder and a OR Gate
borrow out D = Ci (Ai  Bi)

borrow out Ci+1=Ai’BiCi’+Ai’Bi’Ci

+CiA’iBi+AiBiCi
=Ci(Ai’Bi’+AiBi)
+A’iBi(Ci+Ci’)

=Ci(Ai Bi)’+A’iBi
Ci

Ai Di
Bi

C i+1

half subtractor
half subtractor
Mode Controlled Full Adder/Subtractor
 Controlled Full Adder/Subtractor
Ci

Ai Di
Bi

i+
C1
E

E = 0: Full adder
E = 1: Full subtractor
X-OR Gate as NOT Gate
 N-Bit Adder/Subtractor
4-bit Subtractor: E = 0
A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder

C3 C2 C1

C4 SD 3 SD 2 SD 1 SD 0

For
E = 0: 4-bit adder
E = 1: 4-bit subtractor
 4-bit Subtractor: E = 1
A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder

C
3
C2 C1
+1

C4 SD 3 SD 2 SD 1 SD 0

Add A to !B (one’s complement) plus 1

That is, add A to two’s complement of B; D = A - B

 BCD Codes
 BCD Code (Binary-Coded Decimal):
 Also called an 8421 Code due to the decimal weight of each bit position .
 A code used to represent each decimal digit of a number by a 4-Bit Binary
Value.
 Valid Digits for 0 to 9 are 0000 to 1001.
 The binary codes 1010 to 1111 are invalid
 Each digit is a 4-Bit valid Binary group:
 (84)10 = 1000 0100
 (4987)10 = 0100 1001 1000 0111BCD

BCD Adder Circuit

 A Parallel Adder circuit is one whose output sum is in groups of 4 bits and
each representing a BCD (8421) Digit.
 Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B.
 Sum is input to the four-bit input of a Binary-to-BCD Code Converter.
 BCD (Decimal) adder
 When dealing with decimal numbers BCD code is used.
 A BCD adders requires at least 9 inputs 4+4= 8 for (two BCD numbers and
1 for previous carry)
 A BCD adders has 5 outputs (4 for BCD sum and 1 for carry).
 BCD adder: each input does not exceed 9, the output can not exceed 19
 Largest one bit decimal numbers presented in BCD is 9
Decimal Binary BCD
9 1001 1001
 Largest number obtained using addition of two one bit BCD numbers
Amax +Bmax+1 (Cin) = 9 +9+1 =19
 Decimal Binary BCD
19 10011 (0001)(1001)
1 9

48
 BCD (Decimal) adder
 Decimal numbers should be represented in binary code number.
 Suppose we apply two BCD numbers to a binary adder then:
 The result will be in binary and ranges from 0 through 19.
 Let Binary sum: K(carry) Z8 Z4 Z2 Z1
 and BCD sum: C(carry) S8 S4 S2 S1
 For numbers equal or less than 1001 binary and BCD are identical.
 For numbers more than 1001, we should add 6(0110) to binary to
get BCD.
example: 10011(binary 19)
+110 (ADD 6 to correct)
------------------
11001(BCD) =19
.

49
 BCD (Decimal) adder
Direct (Binary sum) (BCD converted sum)
K P 3 P2 P1 P0 C S 3 S2 S1 S0
• We can obtain the sums
0 0 0 0 0 0 0 0 0 0
in two stages. 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
• First, list all possible 0 0 1 0 0 0 0 1 0 0
outputs from the direct 0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
1
1
0
sum of the decimal 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
digits, then ….. 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
• Beside each sum place 0 1 0 1 1 1 0 0 0 1
the expected values of 0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
the sum bits and the 0 1 1 1 0 1 0 1 0 0
carry out bit. 0 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0
• The first-stage sums
divide into two groups: 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
– the first ten sums 0 0 1 0 0 0 0 1 0 0
produce the correct 0 0 1 0 1 0 0 1 0 1
final sum and carry 0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
bit patterns 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
• 98 = 1001 1000
• 89= 1000 1001
•
• 1 0010 0001= 121
• 0110 0110
• 1 1000 0111
•
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0

• The first-stage sums 0 0 0 0 0 0 0 0 0 0

divide into two groups: 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
– the first ten sums 0 0 1 0 1 0 0 1 0 1
produce the correct 0 0 1 1 0 0 0 1 1 0
final sum and carry 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
bit patterns 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
– the last ten sums 0 1 0 1 1 1 0 0 0 1
are all incorrect by 0 1 1 0 0 1 0 0 1 0
the same amount, 0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
they should have 0 1 1 1 1 1 0 1 0 1
6 added to them to
1 0 0 0 0 1 0 1 1 0
produce the correct 1 0 0 0 1 1 0 1 1 1
final bit patterns. 1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0

• The first-stage sums 0 0 0 0 0 0 0 0 0 0

divide into two groups: 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
– the first ten sums 0 0 1 0 1 0 0 1 0 1
produce the correct 0 0 1 1 0 0 0 1 1 0
final sum and carry 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
bit patterns 0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
– the last ten sums 0 1 0 1 1 1 0 0 0 1
are all incorrect by 0 1 1 0 0 +6= 1 0 0 1 0
the same amount, 0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
they should have 0 1 1 1 1 1 0 1 0 1
6 added to them to
1 0 0 0 0 1 0 1 1 0
produce the correct 1 0 0 0 1 1 0 1 1 1
+6=
final bit patterns. 1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0
• The condition used to
0 0 0 0 0 0 0 0 0 0
identify and control the 0 0 0 0 1 0 0 0 0 1
correction process is 0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
expressed in terms of 0 0 1 0 0 0 0 1 0 0
the carry-out bit, C: 0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
C = K + P3 P2 + P3 P1 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0
• The condition used to
0 0 0 0 0 0 0 0 0 0
identify and control the 0 0 0 0 1 0 0 0 0 1
correction process is 0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
expressed in terms of 0 0 1 0 0 0 0 1 0 0
the carry-out bit, C: 0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
C = K + P3 P2 + P3 P1 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
• Thus, if C = 0 then no 0 1 0 1 1 1 0 0 0 1
correction is applied. 0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1

1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
 BCD (Decimal) adder
K P 3 P2 P1 P0 C S 3 S2 S1 S0
• The condition used to
0 0 0 0 0 0 0 0 0 0
identify and control the 0 0 0 0 1 0 0 0 0 1
correction process is 0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
expressed in terms of 0 0 1 0 0 0 0 1 0 0
the carry-out bit, C: 0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
C = K + P3 P2 + P3 P1 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1

0 1 0 1 0 1 0 0 0 0
• Thus, if C = 0 then no 0 1 0 1 1 1 0 0 0 1
correction is applied. 0 1 1 0 0
+6=
1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
• If C = 1, then 6 is added 0 1 1 1 1 1 0 1 0 1

directly to the initial sum 1 0 0 0 0 1 0 1 1 0

bits PJ . 1
1
0
0
0
0
0
1
1
0
+6= 1
1
0
1
1
0
1
0
1
0
1 0 0 1 1 1 1 0 0 1
 BCD adder
Numbers that need correction (add 6) are:
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)

Decides to add 6?

Adds 6

58
BCD adder
 Multiplexers
Multiplexer is a general circuit that produces a single output signal for n
number of input signals
– The output is equal to one of several input signals to the circuit
– The multiplexer selects which input signal is used as an output signal
based on the value represented by a few more input signals, called
select signals or select control lines
– The control lines S0, S1, and S2 determine which of eight other input
lines (D0 through D7) are routed to the output (F)

8:1 Multiplexers