Advanced_VLSI_Modified_Presentation (1)

SEMINAR - ADVANCED VLSI
Procedural Statements and Routines: Task overview, routine

arguments,
returning from a routine.
~SAI SAGAR S
P-
1RF21EC041
TABLE OF CONTENTS
1. Introduction to VLSI Procedural Statements:

VLSI design uses procedural statements to define how circuits behave, similar
to commands in programming.
2. Task overview
Routine Arguments:
Arguments are inputs or outputs for tasks or functions. They let data flow into
and out of routines, classified as input, output, or inout.
4. Common coding Errors
5. Returning from a routine and tasks
6. Default values
7. Passing arguments by name

Introduction to VLSI Procedural Statements:
VLSI design uses procedural statements to define how circuits

behave, similar to commands in programming.
What are Procedural Statements?

○ SystemVerilog procedural statements define the behavior of
code, similar to statements in traditional programming
languages.
○ They allow designers to describe the functionality of digital
systems at various levels of abstraction
○ Common types: always, initial, if-else, case, loops, etc.
○ Importance: Used to model digital circuits behaviorally and
execute tasks/functions.
TASKS IN SYSTEMVERILOG:
Tasks are similar to functions in other programming languages but are distinct
in that they can perform complex actions, including interactions with
simulation time, and can return multiple outputs through output or inout
arguments.
Key Characteristics of SystemVerilog Tasks:

- Timing Control: Tasks can include timing controls like `#delay`, `@event`, or
`wait`, which makes them suitable for operations that need to interact with
simulation time.
- Return Values: Unlike functions, tasks do not return a single value. Instead,
they pass values back using òutput` or ìnout` arguments.
- Multiple Inputs and Outputs: Tasks can accept multiple input, output, and
inout arguments, allowing them to modify multiple values.
- No Return Value: Since tasks don’t return values like functions, they’re
generally used for sequences of actions rather than calculations.
When to Use a Task in SystemVerilog

SYNTAX:
task <task_name> (input <type> arg1, output <type> arg2,
inout <type> arg3);
// Task body with procedural statements
endtask
EXAMPLE:
task generate_clock_pulse(output bit clk);
clk = 1;
#5 clk = 0; // Delay for 5 time units
endtask
● Types of Tasks:
○ Non-blocking: Executes and allows the simulation to proceed concurrently.
○ Blocking: Pauses execution until the task is completed.
ROUTINE ARGUMENTS:
Routine arguments refer to the parameters passed to functions or tasks.

These arguments define how data is passed into and out of the routines, and
they can be specified with several different types: ìnput`, òutput`, and ìnout`.
Routine Arguments:
1. Input Arguments (ìnput`)
- Used to pass values into a routine.
- The value is received by the routine, but it cannot be modified within the
routine.
2. Output Arguments (òutput`)

- Used to return data from the routine to the caller.
- Values assigned to òutput` arguments within the routine are passed back
3. Inout Arguments (ìnout`)
- Allows bidirectional data flow, meaning the argument can be read and
modified within the routine.
- The caller provides an initial value that may be modified by the routine and
passed back.
- Often used when the caller's variable needs to be updated within the
routine.
Routine Arguments:
Arguments are specified in the routine header, and their data types must be
declared. SystemVerilog supports a variety of data types for routine
arguments, including basic types like `bit` and `logic`, as well as complex types
like arrays, structures, and classes.
- Functions can only have ìnput` arguments; they cannot have òutput` or
SYNTAX FOR ROUTINE
ARGUMENTS
For tasks:
Example of Routine Argument
task my_task(input logic a, output int b, Usage
inout bit c);
// Task body
task compute_sum(input int a,
endtask input int b, output int sum, inout
int counter);
For functions: sum = a + b;
function int my_function(input int a, counter += 1; // Increment
input int b); counter each time the task is
called
// Function body
endtask
endfunction
Common Coding Errors:
Ensure each argument's type is clearly stated (e.g., input or output) to avoid
unexpected behavior.
In SystemVerilog, one common coding mistake is forgetting that the

argument type is sticky, meaning that the argument type of the current
argument can be carried over from the previous one if not explicitly declared
For example
task my_task(input int a, b, c);
// b and c are also treated as inputs of type int because a is defined as such.
endtask
To avoid sticky types, always declare both the direction (input, output,
inout, ref) and the data type explicitly for each argument in tasks and
functions. For example:
task my_task(input int a, input int b, input int c);
// Now, each argument has an explicit declaration.
endtask
Returning from Routines:
Functions can return a value directly, while tasks can end early with 'return' without giving
back a value.
● The return statement allows a routine (task or function) to immediately terminate

and optionally return a value (for functions). This is a departure from older Verilog
versions, where a function had to complete its entire body to return a value.
Example:
function int calculate_sum(input int a, b);
if (a < 0 || b < 0) begin
return -1; // Return early if inputs are invalid
end
return a + b; // Return the sum
endfunction
Returning from Tasks:
● Tasks in SystemVerilog do not return values but may still use the
return statement to terminate execution early. This can be useful
in cases where the task encounters an error or when the required
operation is complete before the end of the task body.
task send_data(input bit[7:0] data);
if (data == 8'h00) begin
$display("Invalid data, aborting.");
return; // Exit the task early
end
// Continue with sending data...
endtask
Using Typedef for Arrays:
To return arrays from functions, use typedef to create array types. It

keeps the code clean, especially with complex arrays.typedef
(Recommended Approach)
To return arrays from a function, it's best to use typedef to define the
array type. This simplifies the function definition and keeps your code
readable, especially when dealing with multi-dimensional or complex
arrays.
// Define a 1D array type with 10 integer elements
typedef int int_array_t[10];
// Function returning an array of integers

Default Argument Values:
Use default values for arguments to simplify calls when you don't
need to change every argument.
As your testbench grows in sophistication, you may want to add
additional controls to your code but not break existing code.
In SystemVerilog you can specify a default value that is used if you
leave out an argument in the call.
The following example adds low and high arguments to the print_csm
function so you can
print a checksum of a range of values.
You can call this function in the following ways, as shown in the sample . Note
that the first call is compatible with both versions of the print_csm routine.
Using a default value of −1 (or any out-of-range value) is a good way to see if the
call specified a value.
A Verilog for loop always executes the initialization ( int i=low ), and test
( i<=high ) before starting the loop. Thus, if you accidentally passed a low value that
was larger than high or the array size, the for loop would never execute the body.
Passing Arguments by Name:
For tasks or functions with many arguments, specify only the ones
you
In theneed by naming
SystemVerilog them
LRM that explicitly.
the arguments to a task or function are
sometimes called “ports,” just like the connections for a module.
If you have a task or function with many arguments, some with default values,
and you only want to set a few of those arguments, you can specify a subset by
specifying the name of the routine argument with a port-like syntax, as shown

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SEMINAR - ADVANCED VLSI

Procedural Statements and Routines: Task overview, routine

1. Introduction to VLSI Procedural Statements:

4. Common coding Errors

5. Returning from a routine and tasks

7. Passing arguments by name

VLSI design uses procedural statements to define how circuits

What are Procedural Statements?

Key Characteristics of SystemVerilog Tasks:

When to Use a Task in SystemVerilog

Routine arguments refer to the parameters passed to functions or tasks.

2. Output Arguments (`output`)

In SystemVerilog, one common coding mistake is forgetting that the

● The return statement allows a routine (task or function) to immediately terminate

To return arrays from functions, use typedef to create array types. It

// Define a 1D array type with 10 integer elements

typedef int int_array_t[10];

// Function returning an array of integers

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