Memory Organization 12-1

 Memory Hierarchy
 Memory hierarchy in a computer system :
 Main Memory : memory unit that communicates directly with the CPU (RAM)
 Auxiliary Memory : device that provide backup storage (Disk Drives)
 Cache Memory : special very-high-speed memory to increase the processing
speed (Cache RAM)
Auxiliary memory
Magnetic
tapes
Main
I/ O proc essor
memory
Magnetic
disks

C ac he
C PU
memory

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Memory Organization 12-2

 Multiprogramming
 enable the CPU to process a number of independent program concurrently
 Memory Management System :
 supervise the flow of information between auxiliary memory and main memory

 Memory Hierarchy is to obtain the highest possible access speed while minimizing
the total cost of the memory system

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Random Access Memory (RAM) 12-3

 RAM Chips

 Static RAM
• Consists of Flip-flops to store binary information.
• Static RAM is easier to use and having short Read/Write cycles
• Used mostly in Cache memory.

 Dynamic RAM
 Stores binary information in the form of electric charge stored inside the
capacitor.
 The capacitors are provided by MOS transistors.
 Refreshing circuit is required to refresh the memory.
• Dynamic RAM offers reduced power consumption and large storage
capacity.
• It is used to construct main memory.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Static RAM Vs Dynamic RAM 12-4

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Main Memory
12-5
MAIN MEMORY
RAM and ROM Chips
Typical RAM chip
Chip select 1 CS1
Chip select 2 CS2
Read RD 128 x 8 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedence

Typical ROM chip

Chip select 1 CS1
Chip select 2 CS2
512 x 8 8-bit data bus
ROM
9-bit address AD 9

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Main Memory
12-6
MEMORY ADDRESS MAP
Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexadecimal Address bus

Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
1 x x x x x x x x x
ROM 0200 - 03FF

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Main Memory
12-7
CONNECTION OF MEMORY TO CPU
Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2
RD 128 x 8 Data
RAM 4
WR
AD7

CS1
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Numerical Problems 12-8

Q1. a) How many 128x8 RAM chips are needed to provide a memory capacity of 2048 bytes.
b) How any lines of the address bus must be used to access 2048 bytes of memory. How
many of these lines will be common to all chips.
c) How many lines must be decoded for chip select? Specify the size of decoders.

Q2. Extend the memory system of Fig.1 to 4096 bytes of RAM and 4096 bytes of ROM. List
the memory-address map and indicate what size decoders are needed.

Q3. A computer employs RAM chips of 256x8 and ROM chips of 1024x8. The computer
system needs 2K bytes of RAM, 4K bytes of ROM, and four interface units each with four
registers. A memory-mapped I/O configuration used. The two highest-order bits of the address
bus are assigned 00 for RAM, 01 for ROM, and 10 for interface registers.

How many RAM and ROM chips are needed.

Draw a memory-address map for the system.
Give the address range in hexadecimal for RAM, ROM and interface.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-9

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Cache Memory 12-10

 12-5 Cache Memory

 Locality of Reference
 the references to memory tend to be confined within a few localized
areas in memory

 Cache Memory : a fast small memory

 keeping the most frequently accessed instructions and data in the fast
cache memory

 Hit Ratio
 the ratio of the number of hits divided by the total CPU references (hits +
misses) to memory
» hit : the CPU finds the word in the cache
» miss : the word is not found in cache (CPU must read main
memory)

 A computer with cache access time of 100ns, a main memory access time of
1000 ns, a hit ratio of 0.9 is having average access time of 200ns.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Types of Mapping of Cache Memory 12-11

 Mapping
 The transformation of data from main memory to cache memory
» 1) Associative mapping
» 2) Direct mapping
» 3) Set-associative mapping

 Associative Memory:
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word
» CPU sends a 15-bit address to cache
 Hit : CPU accepts the 12-bit data from cache

 Miss : CPU reads the data from main memory (then data is

written to cache)

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Associative Memory 12-12

Main memory
C PU
32K× 12 C ac he memory
512× 12

C P U address(15 bits)

Argument register

Address D ata

0 1 0 0 0 3 4 5 0

0 2 7 7 7 6 7 1 0

2 2 3 4 5 1 2 3 4

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Direct Mapping 12-13

Direct mapping :
n bit memory address
Tag field (n - k) : Index field (k)
2k words cache memory + 2n words main memory
Tag = 6 bit (15 - 9), Index = 9 bit

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Direct Mapping 12-14

 Direct mapping cache with block size of

Memory Index 8 words :
address Memory data address Tag Data
» 64 block x 8 word = 512 cache words
000000 1220 000 00 1220 size

Index Tag Data 6 6 3

00777 2340 000 01 3450 Tag Block Word

Block 0
01000 3450 007 01 6578
Index
010
Block 1
01777 4560 777 02 6710
017
02000 5670
(b) C ache memory

02777 6710

770 02
Block 63
777 02 6710
(a) Main memory

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Set-Associative Mapping 12-15

Set-associative mapping : (two-way)

Index Tag D ata Tag D ata

000 0 1 3 4 5 0 0 2 5 6 7 0

777 0 2 6 7 1 0 0 0 2 3 4 0

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-16

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-17

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-18

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-19

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Questions 12-20

 A two-way set associative cache memory uses blocks of four words. The cache
can accommodate a total of 2048 words from main memory. The main memory
size is 128Kx32. Formulate all pertinent information required to construct the
cache memory. What is the size of cache memory.

 A computer has a memory unit of 64Kx16 and a cache memory of 1K words.

The cache uses direct mapping with a block size of four words. How many bits
are there in the tag, index, block, and words fields of the address format. How
many bits are there in each word of cache, and how are they divided into
functions? Include a valid bit. How many blocks can the cache accommodate?

 The access time of a cache memory is 100ns and that of main memory is
1000ns. It is estimated that 80 percent of the memory requests are for read and
the remaining 20 percent for write. The hit ratio for read access only is 0.9. A
write-through procedure is used. What is the average access time of the system
considering only memory read cycles. What is the average access time of the
system for both read and write requests. What is the hit ratio considering the
write requests also.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Answer 12-21

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Answer 12-22

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-23

 Replacement Algorithm : cache miss or full

 1) LRU (Least Recently Used):
 2) Random Replacement:
 3) FIFO (First-In First-Out) :

 Writing to Cache :
» 1) Write-through :
» 2) Write-back :

 Cache Initialization
 Cache is initialized :
» 1) When power is applied to the computer
» 2) When main memory is loaded with a complete set of programs
from auxiliary memory
» 3) Cache is initialized by clearing all the valid bits to 0.
 Valid bit
» Indicate whether or not the word contains valid data

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Virtual Memory
12-24
VIRTUAL MEMORY
Give the programmer the illusion that the system has a very large memory,
even though the computer actually has a relatively small main memory

Address Space(Logical) and Memory Space(Physical)

address space memory space

virtual address Mapping

(logical address) physical address

address generated by programs actual main memory address

Address Mapping
Memory Mapping Table for Virtual Address -> Physical Address
Virtual address

Virtual Memory Main memory

address address Main
mapping memory
register table register

Physical
Address
Memory table Main memory
buffer register buffer register

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Virtual Memory
12-25
ADDRESS MAPPING
Address Space and Memory Space are each divided
into fixed size group of words called blocks or pages
1K words group Page 0
Page 1
Page 2
Address space Memory space Block 0
Page 3
N = 8K = 213 M = 4K = 212 Block 1
Page 4
Block 2
Page 5
Block 3
Page 6
Page 7
Organization of memory Mapping Table in a paged system
Page no. Offset
1 0 1 0 1 0 1 0 1 0 0 1 1 Virtual address

Table Presence
address bit
000 0 Main memory
001 11 1 Block 0
010 00 1 Block 1
011 0 01 0101010011 Block 2
100 0 Block 3
Main memory
101 01 1 address register
Memory page table 110 10 1
111 0 MBR

01 1

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Virtual Memory
12-26
PAGE REPLACEMENT ALGORITHMS
FIFO Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 4 4 4 0 0 0 7 7 7
0 0 0 3 3 3 2 2 2 1 1 1 0 0
1 1 1 0 0 0 3 3 3 2 2 2 1
Page frames

FIFO algorithm selects the page that has been in memory the longest time

Optimal Replacement (OPT) - Lowest page fault rate of all algorithms

Replace that page which will not be used for the longest period of time
Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 2 2 7
0 0 0 0 4 0 0 0
1 1 3 3 3 1 1

Page frames

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Virtual Memory
12-27
PAGE REPLACEMENT ALGORITHMS
LRU
- OPT is difficult to implement since it requires future knowledge

Replace that page which has not been

used for the longest period of time

Reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 4 4 4 0 1 1 1
0 0 0 0 0 0 3 3 3 0 0
1 1 3 3 2 2 2 2 2 7
Page frames

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-28

 A virtual memory system has an address space of 8K words, a memory

space of 4K words and page & block sizes are of 1K words. The
following page is referenced in memory: 4 2 0 1 2 6 1 4 0 1 0 2 3 5 7.
Determine the four pages that are resident in main memory after each
page reference change if page replacement algorithm is : FIFO, LRU,
Optimal.

 An address space is specified by 24 bits and the corresponding memory

space by 16 bits. How many words are there in the address space. How
many words are there in the memory space. If a page consists of 2K
words, how many pages and blocks are there in the system?

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-29

Secondary Storage

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Hard-disk Organization 12-30

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Magnetic Hard Disks 12-31

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Organization of Data on a Disk 12-32

Sector 0, track 1
Sector 3, track n
Sector 0, track 0

Organization of one surface of a disk.

Access Time:
Seek time: Time required to move the R/W head to the proper track.
Rotational latency: Time required to move the starting position of sector under the
read/write head.
Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.
 Optical
Disks Aluminum Acrylic Label
12-33

Pit Land Polycarbonate plastic

(a) Cross-section

Pit Land

Reflection Reflection

No reflection

Source Detector Source Detector Source Detector

(b) Transition from pit to land

0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0

(c) Stored binary pattern

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Optical Disks 12-34

 CD is 120 mm in diameter.
 15 mm hole in the center.
 Data stored on tracks that cover the area from 25 mm radius
to 58 mm radius.
 There are more than 15,000 tracks.
 Spiral structured were unraveled will be more than 5
KM long !
 Basic access speed is 1X, 75 sectors per second.
 CD-RW:
 Consists of alloy of silver, indium, antimony & tellurum.
 When heated above 500c, it absorbs light.(Amorphous state)
 When heated to 200c, it goes in crystalline state and allows
light to pass through.
Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.
 Magnetic Tape Systems 12-35

File File
mark File
mark
• •
• • 7 or 9
• • bits
• •

File gap Record Record Record Record

gap gap

Figure 5.33. Organization of data on magnetic tape.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Traditional Memory Architecture 12-36

Processor Memory
k-bit
address bus
MAR
n-bit
data bus
Up to 2k addressable
MDR locations

Word length = n bits

Control lines
( R / W , MFC, etc.)

Figure 5.1. Connection of the memory to the processor.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Internal Organization of Memory Chips 12-37

b7 b¢7 b1 b¢1 b0 b¢0

W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2 • • • • • •

A3

W15
•
•
•

16 words of 8 bits each: Sense / Write Sense / Write Sense / Write R/W
circuit circuit circuit
16x8 memory org.. CS

It has 16 external
connections: addr. 4, data
Data input b7 b1 b0
8, control: 2,
/output lines:
power/ground: 2
Figure 5.2. Organization of bit cells in a memory chip.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-38
A 2D Memory Chip

5-bit row
address W0
W1
32 X 32
5-bit
decoder memory cell
array
W31
Sense/ Write
circuitry

10-bit
address
32-to-1
R/ W
output multiplexer
and
CS
input demultiplexer

5-bit column
address
Data
input/output

Figure 5.3. Organization of a 1K  1 memory chip.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Some examples 12-39

 For example:

 4MB chip may have 512K X 8 organization, 19 address and 8 data lines.

 Also 2^32 generates—4,294,967,296 values. Can address 4GB

locations.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Static RAM 12-40

 The circuits are capable of retaining their state as long as power

is applied.
Figure 5.4. A static RAM cell.

b b¢

T1 T2
X Y

Word line

Bit lines

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Dynamic RAMs 12-41

 Static RAMs are fast, but they cost more area and are more expensive.

 Dynamic RAMs (DRAMs) are cheap and area efficient, but they can not
retain their state indefinitely – need to be periodically refreshed.

Bit line

Word line

T
C

Figure 5.6. A single-transistor dynamic memory cell

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.
 ROM Technology 12-42

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-43
Read-Only-Memory (PROM)

Bit line

Word line

T
Not connected to store a 1
P Connected to store a 0

Figure 5.12. A ROM cell.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Read-Only-Memory 12-44

 PROM: Programmable ROM

 Programmability is achieved by inserting a fuse at point P.

 EPROM: Erasable, Programmable ROM

 Here, at point P special transistor is used which works as
normal transistor or disabled transistor.

 EEPROM: Electrically Erasable ROM.

 It can be programmed and erased electrically by applying
appropriate voltages.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Organization 12-45

 Peripheral Devices: Input & Output devices attached to computer are

called Peripheral.

Input Devices:
 Keyboard, Optical devices: Card reader, Bar code reader etc.
 Magnetic Input Devices: Magnetic stripe reader
 Screen Input Devices: Touch screen, Light pen etc.
Output Devices:
 Keyboard, Optical devices: Card reader, Bar code reader etc.
 Peripherals that provide auxiliary storage are magnetic tape and
magnetic disk.
 Input and output devices communicate alphanumeric information
by using ASCII 7bit code.
 To use computer efficiently, large number of programs and data
must be prepared in advance for execution with computer.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Interface 12-46

 I/O interface provides a method for transferring information

between internal storage and external I/O devices.
 The purpose of interfacing are as follows:
 Peripherals are electromechanical & electromagnetic devices and
are interacting with electronics devices(CPU).
 Data transfer rate of peripherals is usually slower than transfer rate
of CPU.
 Data codes and formats in peripherals differ from word format in
CPU
 Operating modes of peripherals are different from each other and
each one must be controlled without disturbing other.
 To resolve these differences, computer system includes Interface units
between CPU and peripherals to supervise and synchronize all input
and output transfers.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Interface 12-47

 Each peripheral has its own controller that operates a particular

electromechanical device.
 To communicate with a particular device, the processor places a device
address on the address lines.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Interface 12-48

 When the interface detects it own address, it activates path between

bus lines and the device.

 At the time address is made available in address lines, the processor

provides function code(I/O command) in the control lines.

 Types of I/O command:

 Control command: To activate and inform what to do.
 Status command: To test various status conditions.
 Data Output data: It causes the transfer of data from bus into one of its
registers.
 Data Input Command: Interface receives data from peripheral and
places them on buffer register where it is put into data lines.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 I/O versus Memory Bus 12-49

 In addition to communicating to I/O, processor must also

communicate with memory unit.

 There are three ways that computer buses can be used to

communicate with memory and I/O:
 Use two separate buses, one for memory and one for I/O. (IOP)

 Use one common bus for both memory and I/O but have separate

control lines for each. (Isolated I/O)

 Use one common bus for memory and I/O with common control

lines. (Memory Mapped I/O)

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Isolated I/O 12-50

 The distinction between memory and I/O transfer is made through separate read
and control lines.

 I/O read and I/O write are enabled during I/O transfer and Memory read/write are
enabled during memory transfer.

 In the isolated I/O configuration, CPU have distinct input and output instructions
where each of it will be associated with address of the interface register.

 When the CPU fetches and decodes the I/O instruction, it places the address
associated with the instruction on the common address lines and enables I/O
read or I/O write control line.

 When the CPU fetches and decodes the Memory instruction, it places the
address associated with the instruction on the common address lines and
enables Memory read or Memory write control line.

 The isolated I/O method isolates memory and I/O addresses.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Memory Mapped I/O 12-51

 Here the same address space is used for both memory and I/O. The computer
treats interface register as a part of memory system.

 The assigned address cannot be used for storing memory words, which reduces
memory address range available.

 In a memory-mapped I/O organization, there are no specific, input or output

instruction.

 CPU manipulate I/O data residing in interface registers with the same instruction
used to manipulate memory words.

 Load and store instruction used for reading/writing from memory and can be use
for input or output data from I/O instruction.

 With memory-mapped I/O all instructions that refer to memory are also available
for I/O.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Memory Mapped I/O 12-52

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Modes of Transfer 12-53

 Data transfer between the CPU and the I/O devices may be handled in
variety of modes. Some modes use the CPU as an intermediate path
and others transfer the data directly to and from the memory unit.

 Data transfer to and from peripherals may be handled in three ways:

 Programmed I/O

 Interrupt-initiated I/O

 Direct Memory Access (DMA)

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Programmed I/O 12-54

 Programmed I/O operations are the result of I/O instructions. Each data
item transfer is initiate by an instruction in the program.

 Usually the transfer is to and from a CPU register and peripheral. Other
instructions are needed to transfer data between memory and CPU.

 Once a data transfer is initiated, the CPU is required to monitor the

interface to see when a transfer can again be made.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Programmed I/O 12-55

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Interrupt Initiated I/O 12-56

 In the programmed I/O CPU stays in program loop until the I/O indicates
that it is ready for data transfer.

 This is time consuming process since it makes CPU busy needlessly.

 This can be avoided by using an interrupt facility.

 When the interface determines that device is ready for data transfer, it
generates an interrupt request.

 Upon detecting external interrupt signal, the CPU momentarily stops the
task it is processing.

 It then branches to fulfill the I/O request and return to the original task.
 Based on the concept of Priority Interrupt.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Direct Memory Access (DMA) 12-57

 The transfer of data between a fast storage device such as magnetic

disk and memory often limited to the speed of CPU.

 Removing the CPU and letting the peripheral device manage the
memory bus directly improve speed of transfer.

 Such transfer technique is called Direct Memory Access (DMA).

 A DMA controller takes over the buses to manage the transfer directly
between I/O device and memory.

 During DMA transfer, the CPU is idle and has no control over memory
buses.

 By using Bus Request(BR) and Bus Grant(BG) the buses are released
to DMA controller.
Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.
 DMA 12-58

 Data transfer ways:

 Burst Transfer: Here number of words are transferred in a block.

Example: Magnetic disk.

 Cycle stealing: Allows the DMA controller to transfer one data word
at a time after it must return the control of buses to CPU.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 DMA Controller 12-59

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Initialization of DMA 12-60

 The CPU initializes the DMA by sending the following information

through the data bus.

 The starting address of the memory block where data are

available(for read) or where data are to be stored(for write).

 The word count, which is the number of words in the memory block.

 Control to specify the mode of transfer such as read or write.

 A control to start the DMA transfer.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 DMA Transfer in a computer system 12-61

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Transfer (IOP) 12-62

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Input-Output Transfer (IOP) 12-63

 An IOP takes care of input and output tasks.

 IOP is similar to CPU except IOP can fetch and execute an I/O instruction.
 CPU is usually assigned task of initiating the I/O program and thus IOP.
 The CPU is assigned the task of initiating all operations, but I/O instructions are
executed in IOP.

 When an I/O operation is required, the CPU informs the IOP where to find the
I/O program and then leaves the transfer details to the IOP.

 CPU instructions also test I/O status conditions needed for making decisions on
various I/O activities.
 IOP is also responsible of taking care of data synchronization, formats etc
between CPU and I/O devices.
 In most computers CPU is master and IOP is slave.
 The IOP typically asks for CPU attention by means of Interrupt.
Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.
 Bus Arbitration 12-64

 The device that is allowed to initiate data transfers on the bus at any
given time is called Bus master.

 Bus arbitration is the process by which the next device becomes

Bus master and will do the data transfer.

 Two approaches: Centralized Arbitration and Distributed Arbitration.


Centralized Arbitration

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Types of Interrupt 12-65

 Major types of Interrupt are:

 External Interrupt: It comes from I/O devices, from timing device, or
from any other external source. Example that cause
 Internal Interrupt: It includes register overflow, invalid operation
code, stack overflow etc.
 Software Interrupt or Hardware Interrupt: External and Internal
interrupts are initiated from signals that occur in the hardware of
the CPU. A software interrupt is initiated by executing an
instruction.
 Priority Interrupt: In case several sources will request service
simultaneously, in this case system must decide which device to
service first. For ex: Polling, Daisy Chain.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Buses 12-66

 Data Bus: Bi-directional and transfers data.

 Address Bus: Uni-directional and sends the address.
 Control Bus: R/W, BR,BG etc.

 Bus Structure: Single bus

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Buses 12-67

 Bus Structure: Multi bus

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Synchronous or Asynchronous Data
Transfer 12-68

 Internal operations in a digital system are synchronized by means of

clock pulses supplied by common pulse generator.

 If the registers in the interface share a common clock with the CPU
registers, the transfer is synchronous.

 Asynchronous data transfer requires that control signals be transmitted

between communicating units to indicate the time at which data is being
transmitted.

 Asynchronous data transfer can be accomplished by Strobe &

Handshaking.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Strobe Control 12-69

 Strobe control:
 It employs single control line.
 It can be activated either by source or destination unit.

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 Handshaking 12-70

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.