Computer Organization

(Autonomous)

UNIT II
 SYLLABUS

• Computer Arithmetic: Addition and subtraction –

Addition and Subtraction with Signed Magnitude Data,
Hardware Implementation, Hardware Algorithm, Addition
and Subtraction with Signed 2’s Complement Data,
Multiplication Algorithms – Hardware Implementation for
Signed Magnitude Data, Hardware Algorithm, Booth
Multiplication Algorithm, Array Multiplier, Division
Algorithms - Hardware Implementation for Signed
Magnitude Data, Divide Overflow, Hardware Algorithm,
Floating – point Arithmetic operations – Basic
Considerations, Register Configuration, Addition and
Subtraction, Multiplication, Division.
 INDEX

 Addition and Subtraction of Signed-Magnitude data

 Addition and Subtraction of Signed-2’s Compliment data
 Multiplication of Signed-Magnitude and Signed-2’s Compliment
data
 Array Multiplier
 Division of Signed-Magnitude and Signed-2’s Compliment data
 Floating point Arithmetic operations.
Introduction
• Arithmetic instructions in digital computers manipulate data to
produce results necessary for the solutions of computational problems.
These instructions perform arithmetic calculations and are responsible
for the bulk of activity involved in processing data in a computer.
•The four basic arithmetic operations are
addition,subtraction,multiplication and division.
•From these four basic operations , it is possible to formulate other
arithmetic functions and solve problems by means of numerical
analysis methods.
•An arithmetic processor is the pat of a processor unit that executes
arithmetic operations.
•An arithmetic instruction may specify binary or decimal data, and in
each case the data may be in fixed-point or floating point form.
•Negative numbers may be in signed magnitude or signed compliment
representation.
•Fixed point numbers may represents integers or fractions.
What is algorithm?
The solution to any problem that is stated by a finite number of
well-defined procedural steps is called an Algorithm.

In this class we develop the various arithmetic algorithms and show

the procedure for implementing them with digital hardware
we consider addition,subtraction,multiplication,and division
for the following types of data:
Fixed point binary data in signed-magnitude representation
Fixed point binary data in signed-2’s compliment representation
Floating point binary data
Binary-coded decimal(BCD) data
 Addition and Subtraction
The addition and subtraction algorithm for data represented in
signed magnitude and again data represented in signed-2’s
complement.
It is important to realize that the adopted representation for
negative numbers refers to the representation of numbers in the
register before and after the execution of the arithmetic
operations.

Addition and Subtraction with Signed-magnitude Data:

The representation of numbers in signed-magnitude is familiar
because it is used in everyday arithmetic calculation. The
procedure for adding or subtracting two signed binary numbers
with paper and pencils simple and straight-forward. A review of
this procedure will be helpful for deriving the hardware algorithm.
Cont.……..

 We designated the magnitude of the two numbers by A and B.

when the signed numbers are added or subtracted, we find that
there are eight different conditions to consider, depending on
the sign of the numbers and the operation performed. These
conditions are listed in the first column of the table below.
The other column in the table show the actual operation to be
performed with the magnitude of the numbers.
 The last column is needed to prevent negative zero. In other
words ,when two equal numbers are subtracted, the result
should be +0 not -0.
 The algorithms for addition and subtraction are derived from
the table and can be stated as follows (the words inside
parentheses should be used for the subtraction algorithm)
 Addition (subtraction) algorithm: when the signs of A and B
are identical (different), add the two magnitude and attach the
sign of A to the result. When the sign of A and B are different
(identical),compare the magnitudes.
Addition & Subtraction
Signed - Magnitude
Hardware implementation
To implement the two arithmetic operations with hardware,it is first
necessary that the two numbers be stored in registers. Let A and B
be two registers that hold the magnitude of the numbers, and As and
Bs be two flipflops that hold the corresponding signs. The results of
the operation may be transferred to a third register however, a
saving achieved if the result is transferred into A and As . thus A and
As together from an accumulator register.

Consider now the hardware implementation of the algorithms

above. First, a parallel adder is needed to perform the micro
operation A+B. second, comparator circuit is needed to establish if
A>B, A=B, or A<B. third, two parallel subtractor circuits are needed
to perform the micro operation A-B and B-A. The sign relationship
can be determined from an exclusive-OR gate with As and Bs as
inputs.
Cont.…

Hardware Architecture
Cont.…

Flowchart
Addition and Subtraction with signed2’s
complement data
 The left most bit of binary number represents the sign bit; 0
for positive and 1 for negative. If the sign bit is 1, the
entire the entire number is represented in 2’s compliment
form.
 The addition of two numbers in signed-2’s complement
form consists of adding the number with the sign bits
treated the same as the other bits of the number . A carry
out of the sign bit position is discarded .
 The subtraction consists of first taking the 2’s compliment
of the subtrahend and then adding it to the minuend
 When two numbers of n digits each are added and the sum
occupies n+1 Digits, we say that an overflow occurred.
 When the two carries are applied to an exclusive-OR gate,
the overflow is detected when the output of the gate is
equal to 1.
 Addition & Subtraction
Signed – 2’s Complement

The left most bit in AC and BR represents the sign

bits of the numbers
The over flow flip-flops V is set to 1 if there is an
overflow. The output carry in this case is discarded.
Multiplication algorithms:-
multiplication of two fixed point binary numbers in signed
magnitude representation is done with paper and pencil of
successive shift and add operation

if the multiplier bit is a 1,the multiplicand is copied down; otherwise zero

are copied down.
 Hardware Implementation for Signed-Magnitude data

 When multiplication is implemented in a digital computer, it is

convenient to change the process slightly.
 First instead of providing register to store and add
simultaneously as many binary numbers as there are bits in the
multiplier , as it is convenient to provide an adder for the
summation of only two binary numbers and successively
accumulate the partial products in a register.
 Second instead of shifting the multiplicand to the left, the partial
product is shifted to the right.
 Third when bit is 0 no need to add as it doesn’t alter the result
 Multiplication
Signed - Magnitude

 The hardware for multiplication consists of the equipment shown in fig.

plus two are more registers.
 These registers are together with registers A and B..
 The multiplier stored in the Q register and its sign in Q s The sequence
counter SC is initially set to a number equal to the number of bits in the
multiplier. The counter is decremented by 1 after forming each partial
product
 The sum of A and B forms a partial product which is transferred to the EA
register .
 The shift will be denoted by the statement shr EAQ to designate the right
shift depicted .
Cont.…
 Booth’s algorithm
Booth’s Algorithm gives a procedure for multiplying binary number
in sign 2’s complement form
1. The multiplicand is subtracted from the partial product upon
encountering the first least significant 1 in a string of 1’s in the
multiplier.
2. The multiplicand is added to the partial product upon
encountering the first 0 (provided that there was a previous 1) in a
string of 0’s in the multiplier.
3. The partial product does not change when the multiplier bit is
identical to the previous multiplier bit.
 Multiplication
Signed – 2’s Complement (Booth’s)
Cont.…

Flowchart
Array multiplier
The multiplication of the two binary numbers can be
done with one micro-operation by means of a
combinational circuit that forms the product bits all at
once. This is a fast way of multiplying two numbers
since all it takes is the time for the signals to propagate
through the gate that form the multiplication array.
Division Algorithm
Division of two fixed-point binary numbers in signed magnitude representation is
done with paper and pencil by a process of successive compare ,shift ,and subtract
operations ..
Hardware implantation of signed magnitude data
Example of binary division with digital
hardware

Instead of shifting the divisor to the right, the dividend

or partial remainder, is shifted to the left, thus
leaving the two numbers in the
required relative position,
subtraction may be achieved by adding A to the 2’s
compliment of B.

EAQ is shifted to the left with 0 instead of Qn and the

previous value of E lost.
The divisor is stored in the B register and the double
length dividend is stored in register A and Q
The information about relative magnitude is available
in E. if E=1,it signifies that A ≥B. A quotient bit 1 is
inserted into Qn and the partial remainder is shifted
left to repeat the process. If E=0, it signifies that A<B
so the quotient in Qn remains a 0.
The sign of the remainder is the same as the sign of
Divide overflow

This occurs because any dividend will be greater than or equal

to zero.
Over flow condition is usually detected when a special flip-
flop is set . Which will call it a divide overflow flip-flop and
label it DVF
The occurrence of a divide overflow can be handled in variety
of ways
In some computers it is the responsibility of the programmers
to check if DVF is set after each divide instruction
The occurrence of a divide overflow stopped the computer
and this condition was referred to as a DIVIDE STOP.
The best way to avoid a divide overflow is to use floating
point data
The divide overflow can be handled very simply if numbers
are in floating point representation.
Hardware algorithm
The dividend is in A and Q and the divisor in B. The sign of the
results transferred into Qs to be part of quotient.
A divide overflow condition is tested by subtracting divisor in B
from half of the bits of the dividend stored in A. if A≥B, the
divide overflow flip-flop DVF set and the operation is terminated
prematurely.
By doing the process as shown in the flowchart the quotient
magnitude is formed in register Q and the remainder is found in
the register A.
The quotient sign is in Qs and the sign of the remainder in As is
the same as the original sign of the dividend.