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    Static Timing Analysis

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    Nitish Agarwal
    The document discusses static timing analysis (STA), which checks timing performance by validating all possible signal paths for violations. It is faster than dynamic simulation as it does not require simulating logical operations. The document notes STA is advantageous for its speed and exhaustive coverage but is conservative and can report false paths. It also provides an overview of the inputs to STA like the netlist and constraints, and the output being standard delay format files.

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    Static Timing Analysis

    Uploaded by

    Nitish Agarwal
    1K views12 pages
    The document discusses static timing analysis (STA), which checks timing performance by validating all possible signal paths for violations. It is faster than dynamic simulation as it does not require simulating logical operations. The document notes STA is advantageous for its speed and exhaustive coverage but is conservative and can report false paths. It also provides an overview of the inputs to STA like the netlist and constraints, and the output being standard delay format files.

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    The document discusses static timing analysis (STA), which checks timing performance by validating all possible signal paths for violations. It is faster than dynamic simulation as it does not require simulating logical operations. The document notes STA is advantageous for its speed and exhaustive coverage but is conservative and can report false paths. It also provides an overview of the inputs to STA like the netlist and constraints, and the output being standard delay format files.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    1K views12 pages

    Static Timing Analysis

    Uploaded by

    Nitish Agarwal
    The document discusses static timing analysis (STA), which checks timing performance by validating all possible signal paths for violations. It is faster than dynamic simulation as it does not require simulating logical operations. The document notes STA is advantageous for its speed and exhaustive coverage but is conservative and can report false paths. It also provides an overview of the inputs to STA like the netlist and constraints, and the output being standard delay format files.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 12

    Nitish Agarwal 070907542

    Place Of Internship

    SoC Players

    SoC Flow

    STA is a method of validating the timing performance of a design by checking all possible paths for timing violations. It is much faster than dynamic simulation because it is not necessary to simulate the logical operation of the design

    Timing Need ?
    15% delay

    Mid 80 Scenario
    Most of the input to output delay of the logic is due to gate delay

    85% delay

    50% delay

    Mid 90 Scenario
    Half of input to output delay of the logic is due to wire delay

    50% delay

    Today s Scenario
    80% delay

    Most of input to output delay of the logic is due to wire delay

    20% delay

    STA Advantage
    Speed (orders of magnitude faster than dynamic simulation) Capacity to handling full chip Exhaustive timing coverage Test vectors are not required

    STA disadvantage
    It is pessimistic (too conservative) Reports false paths

    Static Timing Analysis v/s Dynamic Timing Analysis


    Static analysis is performed by calculating all possible delays between points of connectivity in a circuit. Dynamic analysis is only performed on nets that are stimulated by applying vectors to a simulation model.

    Flow Inputs
    Gate-level Netlist Constraints (SDC Standard Design Constraint) Extracted nets (SPEF Standard Parasitic Exchange Format) Libraries (liberty format - .lib)

    Flow Output
    Standard Delay Format (SDF)

    STA INTERACTION
    Synthesis Team APR Team

    constraints

    constraints

    STA Team

    Modes understanding

    Team DFT

    FE Team

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