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Makefile: support UNALIGNED_ACCESS_SUPPORTED for RISC-V #1639

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@Polaris-911 Polaris-911 commented Aug 7, 2025

Description
When building on RISC-V, allow users to opt in to unaligned access by setting the UNALIGNED_ACCESS_SUPPORTED This appends
-DUNALIGNED_ACCESS_SUPPORTED to CFLAGS, which in turn enables LZ4_FORCE_MEMORY_ACCESS=2 under RISC-V only.

Usage:
make UNALIGNED_ACCESS_SUPPORTED=1

Reason for modification
During testing, we found that direct access to unaligned memory is currently the best method on RISC-V, similar to the method on ARMv6. However, not all RISC-V servers support unaligned memory, and the GCC compiler does not have a macro to distinguish whether unaligned memory is supported. Therefore, we chose to add a new macro to manually allow users to enable direct access on RISC-V servers that support unaligned memory to achieve performance improvement.

Testing
Testing of this modification on a RISC-V server found that the compression rate increased by 30%. The test data is as follows:
Tool: lzbench
Unaligned_Access_Supported disabled:

lzbench 2.1 | GCC 13.2.1 | 64-bit Linux |

Compressor name         Compress. Decompress. Compr. size  Ratio Filename
lz4 1.10.0               96.8 MB/s   206 MB/s   100881340  47.60 ../silesia.tar
[Params] cIters=5 dIters=5 cTime=0.0 dTime=0.0 chunkSize=1706MB cSpeed=0MB

Unaligned_Access_Supported enabled:

lzbench 2.1 | GCC 13.2.1 | 64-bit Linux |

Compressor name         Compress. Decompress. Compr. size  Ratio Filename
lz4 1.10.0                124 MB/s   209 MB/s   100881340  47.60 ../silesia.tar
[Params] cIters=5 dIters=5 cTime=0.0 dTime=0.0 chunkSize=1706MB cSpeed=0MB

When building on RISC-V, allow users to opt in to unaligned access
by setting the UNALIGNED_ACCESS_SUPPORTED env var. This appends
-DUNALIGNED_ACCESS_SUPPORTED to CFLAGS, which in turn enables
LZ4_FORCE_MEMORY_ACCESS=2 under RISC-V only.

Usage:

    make UNALIGNED_ACCESS_SUPPORTED=1
@t-mat
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t-mat commented Aug 7, 2025

Hi @Polaris-911 thanks for your effort and the PR!

For future contributors, could you provide your environment and actual GCC compiler options?
I think Basic info would be enough for now.

cat /proc/device-tree/model
uname -a

Since RISC-V processors are extremely diverse, I also hope RISC-V consortium will define standard hadware feature macro or special vendor pragmas. Dynamic dispatch may be great, but for embeded platforms, they may not be able to accept it.

@Polaris-911
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Hello, my environment information is as follows

[root@fedora-riscv lzbench-master]# uname -a
Linux fedora-riscv 6.1.31 #1 SMP Thu Jun 15 01:30:00 CST 2023 riscv64 GNU/Linux
[root@fedora-riscv lzbench-master]#  cat /proc/device-tree/model
Sophgo Mango

During the test, I compiled lzbench with the following commands:

make DONT_BUILD_TORNADO=1 -j
make UNALIGNED_ACCESS_SUPPORTED=1 DONT_BUILD_TORNADO=1 -j

Performance has been improved by adding the option UNALIGNED_ACCESS_SUPPORTED=1

Thank you for your suggestion. I will continue to look for other better implementation methods. Under the current limited conditions, this is the most appropriate modification I can think of. It can ensure that we have a significant improvement on risc-v without affecting other architectures.

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2 participants