Hardware and Computer Systems Engineer
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University of Ioannina
- Ioannina, Greece
- @pantelisEVs
- in/patsaoglou-pantelis
Highlights
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JTAG-IEEE-1149.1
JTAG-IEEE-1149.1 PublicBasic JTAG standard implementation in Verilog and integration with a CUT
Verilog 3
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LRS-NODE-1
LRS-NODE-1 PublicIoT node based on a LoraWAN STM32WLE module used for Environmental Monitoring (Hackathon 2025 follow-up)
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oosCompiler
oosCompiler PublicAn Object Oriented programming language made using the ANTLR Framework to produce a final C source file that gets compiled into binary using GCC
Python 4
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