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nbd168paulburton
nbd168
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paulburton
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MIPS: ath79: make specifying the reference clock in DT optional
It can be autodetected for many SoCs using the strapping options. If the clock is specified in DT, the autodetected value is ignored Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org
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‎arch/mips/ath79/clock.c

Lines changed: 40 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
8080
return clk;
8181
}
8282

83+
static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
84+
{
85+
struct clk *clk = clks[ATH79_CLK_REF];
86+
87+
if (clk)
88+
rate = clk_get_rate(clk);
89+
else
90+
clk = ath79_set_clk(ATH79_CLK_REF, rate);
91+
92+
return rate;
93+
}
94+
8395
static void __init ar71xx_clocks_init(void __iomem *pll_base)
8496
{
8597
unsigned long ref_rate;
@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(void __iomem *pll_base)
90102
u32 freq;
91103
u32 div;
92104

93-
ref_rate = AR71XX_BASE_FREQ;
105+
ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
94106

95107
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
96108

@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(void __iomem *pll_base)
106118
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
107119
ahb_rate = cpu_rate / div;
108120

109-
ath79_set_clk(ATH79_CLK_REF, ref_rate);
110121
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
111122
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
112123
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
113124
}
114125

115-
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
126+
static void __init ar724x_clocks_init(void __iomem *pll_base)
116127
{
117-
u32 pll;
118128
u32 mult, div, ddr_div, ahb_div;
129+
u32 pll;
130+
131+
ath79_setup_ref_clk(AR71XX_BASE_FREQ);
119132

120133
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
121134

@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
130143
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
131144
}
132145

133-
static void __init ar724x_clocks_init(void __iomem *pll_base)
134-
{
135-
struct clk *ref_clk;
136-
137-
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
138-
139-
ar724x_clk_init(ref_clk, pll_base);
140-
}
141-
142-
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
146+
static void __init ar933x_clocks_init(void __iomem *pll_base)
143147
{
148+
unsigned long ref_rate;
144149
u32 clock_ctrl;
145150
u32 ref_div;
146151
u32 ninit_mul;
@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
149154
u32 cpu_div;
150155
u32 ddr_div;
151156
u32 ahb_div;
157+
u32 t;
158+
159+
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
160+
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
161+
ref_rate = (40 * 1000 * 1000);
162+
else
163+
ref_rate = (25 * 1000 * 1000);
164+
165+
ath79_setup_ref_clk(ref_rate);
152166

153167
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
154168
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
197211
ref_div * out_div * ahb_div);
198212
}
199213

200-
static void __init ar933x_clocks_init(void __iomem *pll_base)
201-
{
202-
struct clk *ref_clk;
203-
unsigned long ref_rate;
204-
u32 t;
205-
206-
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
207-
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
208-
ref_rate = (40 * 1000 * 1000);
209-
else
210-
ref_rate = (25 * 1000 * 1000);
211-
212-
ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
213-
214-
ar9330_clk_init(ref_clk, ath79_pll_base);
215-
}
216-
217214
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
218215
u32 frac, u32 out_div)
219216
{
@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
253250
else
254251
ref_rate = 25 * 1000 * 1000;
255252

253+
ref_rate = ath79_setup_ref_clk(ref_rate);
254+
256255
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
257256
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
258257
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
339338
else
340339
ahb_rate = cpu_pll / (postdiv + 1);
341340

342-
ath79_set_clk(ATH79_CLK_REF, ref_rate);
343341
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
344342
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
345343
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
363361
else
364362
ref_rate = 25 * 1000 * 1000;
365363

364+
ref_rate = ath79_setup_ref_clk(ref_rate);
365+
366366
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
367367
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
368368
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
423423
else
424424
ahb_rate = cpu_pll / (postdiv + 1);
425425

426-
ath79_set_clk(ATH79_CLK_REF, ref_rate);
427426
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
428427
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
429428
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
445444
else
446445
ref_rate = 25 * 1000 * 1000;
447446

447+
ref_rate = ath79_setup_ref_clk(ref_rate);
448+
448449
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
449450
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
450451
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
505506
else
506507
ahb_rate = cpu_pll / (postdiv + 1);
507508

508-
ath79_set_clk(ATH79_CLK_REF, ref_rate);
509509
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
510510
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
511511
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
537537
else
538538
ref_rate = 25 * 1000 * 1000;
539539

540+
ref_rate = ath79_setup_ref_clk(ref_rate);
541+
540542
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
541543
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
542544
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
606608
else
607609
ahb_rate = cpu_pll / (postdiv + 1);
608610

609-
ath79_set_clk(ATH79_CLK_REF, ref_rate);
610611
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
611612
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
612613
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
682683
void __iomem *pll_base;
683684

684685
ref_clk = of_clk_get(np, 0);
685-
if (IS_ERR(ref_clk)) {
686-
pr_err("%pOF: of_clk_get failed\n", np);
687-
goto err;
688-
}
686+
if (!IS_ERR(ref_clk))
687+
clks[ATH79_CLK_REF] = ref_clk;
689688

690689
pll_base = of_iomap(np, 0);
691690
if (!pll_base) {
@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
694693
}
695694

696695
if (of_device_is_compatible(np, "qca,ar9130-pll"))
697-
ar724x_clk_init(ref_clk, pll_base);
696+
ar724x_clocks_init(pll_base);
698697
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
699-
ar9330_clk_init(ref_clk, pll_base);
698+
ar933x_clocks_init(pll_base);
700699
else {
701700
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
702701
goto err_iounmap;
@@ -714,9 +713,6 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
714713

715714
err_clk:
716715
clk_put(ref_clk);
717-
718-
err:
719-
return;
720716
}
721717
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
722718
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);

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