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tursulinjnikula
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drm/i915/pmu: Fix enable count array size and bounds checking
Enable count array is supposed to have one counter for each possible engine sampler. As such, array sizing and bounds checking is not correct and would blow up the asserts if more samplers were added. No ill-effect in the current code base but lets fix it for correctness. At the same time tidy the assert for readability and robustness. v2: * One check per assert. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: b46a33e ("drm/i915/pmu: Expose a PMU interface for perf queries") Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190205130353.21105-1-tvrtko.ursulin@linux.intel.com (cherry picked from commit 26a11de) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
1 parent 3b91a93 commit d8b879b

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3 files changed

+22
-11
lines changed

3 files changed

+22
-11
lines changed

drivers/gpu/drm/i915/i915_pmu.c

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event)
594594
* Update the bitmask of enabled events and increment
595595
* the event reference counter.
596596
*/
597-
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
597+
BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
598+
GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
598599
GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
599600
i915->pmu.enable |= BIT_ULL(bit);
600601
i915->pmu.enable_count[bit]++;
@@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event)
615616
engine = intel_engine_lookup_user(i915,
616617
engine_event_class(event),
617618
engine_event_instance(event));
618-
GEM_BUG_ON(!engine);
619-
engine->pmu.enable |= BIT(sample);
620619

621-
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
620+
BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
621+
I915_ENGINE_SAMPLE_COUNT);
622+
BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
623+
I915_ENGINE_SAMPLE_COUNT);
624+
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
625+
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
622626
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
627+
628+
engine->pmu.enable |= BIT(sample);
623629
engine->pmu.enable_count[sample]++;
624630
}
625631

@@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event)
649655
engine = intel_engine_lookup_user(i915,
650656
engine_event_class(event),
651657
engine_event_instance(event));
652-
GEM_BUG_ON(!engine);
653-
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
658+
659+
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
660+
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
654661
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
662+
655663
/*
656664
* Decrement the reference count and clear the enabled
657665
* bitmask when the last listener on an event goes away.
@@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event)
660668
engine->pmu.enable &= ~BIT(sample);
661669
}
662670

663-
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
671+
GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
664672
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
665673
/*
666674
* Decrement the reference count and clear the enabled

drivers/gpu/drm/i915/i915_pmu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@ enum {
3131
((1 << I915_PMU_SAMPLE_BITS) + \
3232
(I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
3333

34+
#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
35+
3436
struct i915_pmu_sample {
3537
u64 cur;
3638
};

drivers/gpu/drm/i915/intel_ringbuffer.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -415,16 +415,17 @@ struct intel_engine_cs {
415415
/**
416416
* @enable_count: Reference count for the enabled samplers.
417417
*
418-
* Index number corresponds to the bit number from @enable.
418+
* Index number corresponds to @enum drm_i915_pmu_engine_sample.
419419
*/
420-
unsigned int enable_count[I915_PMU_SAMPLE_BITS];
420+
unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
421421
/**
422422
* @sample: Counter values for sampling events.
423423
*
424424
* Our internal timer stores the current counters in this field.
425+
*
426+
* Index number corresponds to @enum drm_i915_pmu_engine_sample.
425427
*/
426-
#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
427-
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
428+
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
428429
} pmu;
429430

430431
/*

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