[RISCV] Failure to use rev8 and 4 byte stores. Possibly due to alignment tracking #152330
Description
With -march=rv32gc_zbb, gcc uses two rev8 instructions and two word sized stores. clang emits shifts and byte stores. https://godbolt.org/z/bWxrnM8rv
#include <stdint.h>
struct a {
uint64_t b;
uint8_t block[64];
};
void c(struct a *ctx) {
uint64_t d = ctx->b;
(ctx->block + 64 - 8)[0] = d >> 56;
(ctx->block + 64 - 8)[1] = d >> 48;
(ctx->block + 64 - 8)[2] = d >> 40;
(ctx->block + 64 - 8)[3] = d >> 32;
(ctx->block + 64 - 8)[4] = d >> 24;
(ctx->block + 64 - 8)[5] = d >> 16;
(ctx->block + 64 - 8)[6] = d >> 8;
(ctx->block + 64 - 8)[7] = d;
}
I believe the issue has something to do with determining alignment of the bytes stores. RISC-V requires strict alignment of word stores. The word store would be aligned, but the compiler isn't able to see it.