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[RISCV] computeKnownBitsForTargetNode - add RISCVISD::SRLW handling #154913

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#155995
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[RISCV] computeKnownBitsForTargetNode - add RISCVISD::SRLW handling#154913
#155995
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backend:RISC-Vgood first issuehttps://github.com/llvm/llvm-project/contribute
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RKSimon
opened on Aug 22, 2025

Mentioned on #148252 - RISCVISD::SRLW can be handled similar to how RISCVISD::SLLW already is

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backend:RISC-Vgood first issuehttps://github.com/llvm/llvm-project/contribute

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