[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence #154952
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@llvm/pr-subscribers-backend-amdgpu Author: Brox Chen (broxigarchen) Changesupdate zext pattern with reg_sequence. This is a follow up from #154211 (comment) Full diff: https://github.com/llvm/llvm-project/pull/154952.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e8b4501226732..ed5df2c55db1b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3106,9 +3106,7 @@ def : GCNPat<
def : GCNPat<
(i64 (DivergentUnaryFrag<zext> i16:$src)),
- (REG_SEQUENCE VReg_64,
- (INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0,
- (S_MOV_B32 (i32 0)), sub1)
+ (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (S_MOV_B32 (i32 0)), sub1)
>;
def : GCNPat<
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arsenm
approved these changes
Aug 23, 2025
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update zext pattern with reg_sequence. This is a follow up from #154211 (comment)