[RISCV] Simplify Zcf/Zce/Zcd Predicates #155035
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This is a big change, trying to simplify our instruction predicates against the instruction spec. The overall approach is this: - Trust RISCVISAInfo to expand Zce/C with F and Zce/Z with D correctly adding `Zcd` and `Zcf`. This will be done by clang. Add more coverage for checking the C+F/C+D combinations specifically. - Simplify the predicates to stop checking if `Subtarget->HasStdExtC()` and `Subtarget->hasStdExtZce()`, trusting the enabled-ness of Zcf/Zcd. - Remove llc/llvm-mc test lines that assume `+c,+f` will be equivalent to `+zcf` (and equivalently for `+zcd`). - Simplify lots of error messages to only point at Zcf/Zcd. - Deprecate the accessors in RISCVSubtarget, for their generated equivalents. There is one breaking change: `.option arch, +zce, +f` no longer enables the Zcf instructions, because don't expand all the implications of extensions in this assembly directive.
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@llvm/pr-subscribers-backend-risc-v Author: Sam Elliott (lenary) ChangesThis is a big change, trying to simplify our instruction predicates against the instruction spec. The overall approach is this:
There is one breaking change: Patch is 39.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/155035.diff 16 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3b738e4cc11a1..96780a51d08fc 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -404,11 +404,9 @@ def FeatureStdExtZcd
"Compressed Double-Precision Floating-Point Instructions",
[FeatureStdExtD, FeatureStdExtZca]>,
RISCVExtensionBitmask<1, 4>;
-
-def HasStdExtCOrZcd
- : Predicate<"Subtarget->hasStdExtCOrZcd()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
- "'C' (Compressed Instructions) or "
+def HasStdExtZcd
+ : Predicate<"Subtarget->hasStdExtZcd()">,
+ AssemblerPredicate<(any_of FeatureStdExtZcd),
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
def FeatureStdExtZcf
@@ -416,6 +414,10 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>,
RISCVExtensionBitmask<1, 5>;
+def HasStdExtZcf
+ : Predicate<"Subtarget->hasStdExtZcf()">,
+ AssemblerPredicate<(any_of FeatureStdExtZcf),
+ "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
def FeatureStdExtZclsd
: RISCVExtension<1, 0,
@@ -431,7 +433,7 @@ def FeatureStdExtZcmp
"sequenced instructions for code-size reduction",
[FeatureStdExtZca]>,
RISCVExtensionBitmask<1, 10>;
-def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
+def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instructions for code-size reduction)">;
@@ -449,14 +451,6 @@ def FeatureStdExtZce
[FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
FeatureStdExtZcmt]>;
-def HasStdExtCOrZcfOrZce
- : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"
- "Subtarget->hasStdExtZce()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
- FeatureStdExtZce),
- "'C' (Compressed Instructions) or "
- "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-
def FeatureStdExtZcmop
: RISCVExtension<1, 0, "Compressed May-Be-Operations",
[FeatureStdExtZca]>,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index c5551fbdec287..451cc9d06a821 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -301,7 +301,7 @@ def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
let Inst{5} = imm{3};
}
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
Sched<[WriteFLD64, ReadFMemBase]> {
bits<8> imm;
@@ -327,7 +327,7 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
}
let DecoderNamespace = "RV32Only",
- Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+ Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
bits<7> imm;
@@ -344,7 +344,7 @@ def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
let Inst{6-5} = imm{7-6};
}
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
bits<8> imm;
@@ -370,7 +370,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
}
let DecoderNamespace = "RV32Only",
- Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+ Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
bits<7> imm;
@@ -500,7 +500,7 @@ def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),
let Constraints = "$rd = $rd_wb";
}
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
Sched<[WriteFLD64, ReadFMemBase]> {
let Inst{4-2} = imm{8-6};
@@ -518,7 +518,7 @@ def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
}
let DecoderNamespace = "RV32Only",
- Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+ Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
let Inst{3-2} = imm{7-6};
@@ -560,7 +560,7 @@ def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),
let Constraints = "$rs1 = $rd";
}
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
let Inst{9-7} = imm{8-6};
@@ -578,7 +578,7 @@ def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
}
let DecoderNamespace = "RV32Only",
- Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+ Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
let Inst{8-7} = imm{7-6};
@@ -648,14 +648,14 @@ def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>;
}
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
}
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
@@ -776,10 +776,10 @@ def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
let Predicates = [HasStdExtZca] in {
def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -790,20 +790,20 @@ def : CompressPat<(LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
let Predicates = [HasStdExtZca, IsRV64] in {
def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
} // Predicates = [HasStdExtZca, IsRV64]
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
let Predicates = [HasStdExtZca] in {
def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -814,10 +814,10 @@ def : CompressPat<(SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
let Predicates = [HasStdExtZca, IsRV64] in {
def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
@@ -907,10 +907,10 @@ def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
(C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
let Predicates = [HasStdExtZca] in {
def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -921,10 +921,10 @@ def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
(C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
(C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
let Predicates = [HasStdExtZca, IsRV64] in {
def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
@@ -953,10 +953,10 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
(C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
let Predicates = [HasStdExtZca] in {
def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -967,10 +967,10 @@ def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
(C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
} // Predicates = [HasStdExtZca]
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
(C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
let Predicates = [HasStdExtZca, IsRV64] in {
def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index f8d33ae8d24ca..f77c245eb4aac 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -211,9 +211,9 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
case RISCV::LD_RV32:
return STI.hasStdExtZclsd();
case RISCV::FLW:
- return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+ return !STI.is64Bit() && STI.hasStdExtZcf();
case RISCV::FLD:
- return STI.hasStdExtCOrZcd();
+ return STI.hasStdExtZcd();
}
}
@@ -235,9 +235,9 @@ static bool isCompressibleStore(const MachineInstr &MI) {
case RISCV::SD_RV32:
return STI.hasStdExtZclsd();
case RISCV::FSW:
- return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+ return !STI.is64Bit() && STI.hasStdExtZcf();
case RISCV::FSD:
- return STI.hasStdExtCOrZcd();
+ return STI.hasStdExtZcd();
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index fd57e02c25d05..05f96bd976f72 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -171,10 +171,15 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca")
bool hasStdExtCOrZca() const { return HasStdExtZca; }
+
+ LLVM_DEPRECATED("Equivalent to hasStdExtZcd", "hasStdExtZcd")
bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
+
+ LLVM_DEPRECATED("Equivalent to hasStdExtZcf", "hasStdExtZcf")
bool hasStdExtCOrZcfOrZce() const {
return HasStdExtC || HasStdExtZcf || HasStdExtZce;
}
+
bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
diff --git a/llvm/test/CodeGen/RISCV/compress-float.ll b/llvm/test/CodeGen/RISCV/compress-float.ll
index d12badd658d6e..8667d3b5fd057 100644
--- a/llvm/test/CodeGen/RISCV/compress-float.ll
+++ b/llvm/test/CodeGen/RISCV/compress-float.ll
@@ -5,27 +5,6 @@
;
; RUN: cat %s > %t.tgtattr
; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \
-; RUN: -disable-block-placement < %t.tgtattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
-; RUN: -disable-block-placement < %t.fnattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \
-; RUN: -disable-block-placement < %t.mixedattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.tgtattr
-; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \
; RUN: -disable-block-placement < %t.tgtattr \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
@@ -44,27 +23,6 @@
; RUN: -disable-block-placement < %t.mixedattr \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.tgtattr
-; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
-; RUN: -disable-block-placement < %t.tgtattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
-; RUN: -disable-block-placement < %t.fnattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
-; RUN: -disable-block-placement < %t.mixedattr \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %s
; This acts as a basic correctness check for the codegen instruction compression
; path, verifying that the assembled file contains compressed instructions when
diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s
index 2bfae212e1fd3..0900f6ee44494 100644
--- a/llvm/test/MC/RISCV/compress-rv32d.s
+++ b/llvm/test/MC/RISCV/compress-rv32d.s
@@ -1,13 +1,3 @@
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding < %s \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding \
@@ -19,16 +9,6 @@
# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+zcd,+d -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding < %s \
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding \
diff --git a/llvm/test/MC/RISCV/compress-rv32f.s b/llvm/test/MC/RISCV/compress-rv32f.s
index 5fc3f41fdf0a5..6ab8e95cc3f26 100644
--- a/llvm/test/MC/RISCV/compress-rv32f.s
+++ b/llvm/test/MC/RISCV/compress-rv32f.s
@@ -1,13 +1,3 @@
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding < %s \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding \
diff --git a/llvm/test/MC/RISCV/option-arch.s b/llvm/test/MC/RISCV/option-arch.s
index 0367ef317e71a....
[truncated]
|
|
This will probably break other frontends like rust that don't use RISCVISAInfo. They just pass -mattr directly. For example, https://github.com/rust-lang/rust/blob/54c581243c977c7662c949b5795c31147f8a60ed/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_linux_gnu.rs |
|
I guess I can file a ticket against Rust? Maybe Zig and Julia too? I'm not sure which other front ends exist. Flang should be using RISCVISAInfo but I will check. |
|
This was referenced Aug 26, 2025
|
I don't think it is a good idea to make every frontend adapt to this. I agree with the comments in the Zig ticket. I've also been thinking about how to do this in the RISCV subtarget constructor. |
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This is a big change, trying to simplify our instruction predicates against the instruction spec.
The overall approach is this:
ZcdandZcf. This will be done by clang. Add more coverage for checking the C+F/C+D combinations specifically.Subtarget->HasStdExtC()andSubtarget->hasStdExtZce(), trusting the enabled-ness of Zcf/Zcd.+c,+fwill be equivalent to+zcf(and equivalently for+zcd).There is one breaking change:
.option arch, +zce, +fno longer enables the Zcf instructions, because we don't expand all the implications of extensions in this assembly directive.