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[AMDGPU] gfx1250 min/max codegen tests. NFC. #155292

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Aug 25, 2025
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[AMDGPU] gfx1250 min/max codegen tests. NFC. #155292

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65 changes: 65 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s

---
name: smax_s64_sv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: smax_s64_sv
; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_SMAX %0, %1
S_ENDPGM 0, implicit %2
...

---
name: smax_s64_vs
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: smax_s64_vs
; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
%0:sgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $sgpr2_sgpr3
%2:vgpr(s64) = G_SMAX %0, %1
S_ENDPGM 0, implicit %2
...

---
name: smax_s64_vv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: smax_s64_vv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_SMAX %0, %1
S_ENDPGM 0, implicit %2
...
65 changes: 65 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
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@@ -0,0 +1,65 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s

---
name: smin_s64_sv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: smin_s64_sv
; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_SMIN %0, %1
S_ENDPGM 0, implicit %2
...

---
name: smin_s64_vs
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: smin_s64_vs
; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
%0:sgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $sgpr2_sgpr3
%2:vgpr(s64) = G_SMIN %0, %1
S_ENDPGM 0, implicit %2
...

---
name: smin_s64_vv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: smin_s64_vv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_SMIN %0, %1
S_ENDPGM 0, implicit %2
...
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
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Expand Up @@ -2,6 +2,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s

---
name: smin_s32_ss
Expand Down
65 changes: 65 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,65 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s

---
name: umax_s64_sv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umax_s64_sv
; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMAX %0, %1
S_ENDPGM 0, implicit %2
...

---
name: umax_s64_vs
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: umax_s64_vs
; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
%0:sgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $sgpr2_sgpr3
%2:vgpr(s64) = G_UMAX %0, %1
S_ENDPGM 0, implicit %2
...

---
name: umax_s64_vv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umax_s64_vv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMAX %0, %1
S_ENDPGM 0, implicit %2
...
65 changes: 65 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,65 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s

---
name: umin_s64_sv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umin_s64_sv
; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...

---
name: umin_s64_vs
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: umin_s64_vs
; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:sgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $sgpr2_sgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...

---
name: umin_s64_vv
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umin_s64_vv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...
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