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@XChy XChy commented Aug 26, 2025

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@XChy XChy requested a review from lukel97 August 26, 2025 10:14
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llvmbot commented Aug 26, 2025

@llvm/pr-subscribers-backend-risc-v

Author: XChy (XChy)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/155389.diff

1 Files Affected:

  • (modified) llvm/docs/RISCV/RISCVVectorExtension.rst (+1-1)
diff --git a/llvm/docs/RISCV/RISCVVectorExtension.rst b/llvm/docs/RISCV/RISCVVectorExtension.rst
index 525b986f98df6..6f64ddb4f329d 100644
--- a/llvm/docs/RISCV/RISCVVectorExtension.rst
+++ b/llvm/docs/RISCV/RISCVVectorExtension.rst
@@ -298,7 +298,7 @@ Register allocation is split between vector and scalar registers, with vector al
 
 There are four register classes for vectors:
 
-- ``VR`` for vector registers (``v0``, ``v1,``, ..., ``v32``). Used when :math:`\text{LMUL} \leq 1` and mask registers.
+- ``VR`` for vector registers (``v0``, ``v1,``, ..., ``v31``). Used when :math:`\text{LMUL} \leq 1` and mask registers.
 - ``VRM2`` for vector groups of length 2 i.e., :math:`\text{LMUL}=2` (``v0m2``, ``v2m2``, ..., ``v30m2``)
 - ``VRM4`` for vector groups of length 4 i.e., :math:`\text{LMUL}=4` (``v0m4``, ``v4m4``, ..., ``v28m4``)
 - ``VRM8`` for vector groups of length 8 i.e., :math:`\text{LMUL}=8` (``v0m8``, ``v8m8``, ..., ``v24m8``)

@XChy XChy changed the title [RVV] Fix typo v32 -> v31 in document [RVV][NFC] Fix typo v32 -> v31 in document Aug 26, 2025
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LGTM. Btw the tag in the commit title should be [RISCV], we don't really use [RVV]

@XChy XChy changed the title [RVV][NFC] Fix typo v32 -> v31 in document [RISCV][NFC] Fix typo v32 -> v31 in document Aug 26, 2025
@XChy XChy merged commit 3d498e5 into llvm:main Aug 26, 2025
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3 participants