[X86] canCreateUndefOrPoisonForTargetNode - add SSE bit logic + VPTERNLOG handling #155600
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…NLOG handling Basic bitlogic operations don't create undef/poison. Its proving really annoying to create proper test coverage for these specific opcodes as they tend to appear in later stages - their presence does help in some upcoming patches (e.g. llvm#152107) and I'd prefer to get them committed early.
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesBasic bitlogic operations don't create undef/poison. Its proving really annoying to create proper test coverage for these specific opcodes as they tend to appear in later stages - their presence does help in some upcoming patches (e.g. #152107) and I'd prefer to get them committed early. Full diff: https://github.com/llvm/llvm-project/pull/155600.diff 1 Files Affected:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9a3e79569df50..ab21cf534b304 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45150,6 +45150,14 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode(
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
switch (Op.getOpcode()) {
+ // SSE bit logic.
+ case X86ISD::FAND:
+ case X86ISD::FOR:
+ case X86ISD::FXOR:
+ case X86ISD::FANDN:
+ case X86ISD::ANDNP:
+ case X86ISD::VPTERNLOG:
+ return false;
// SSE vector insert/extracts use modulo indices.
case X86ISD::PINSRB:
case X86ISD::PINSRW:
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Basic bitlogic operations don't create undef/poison.
Its proving really annoying to create proper test coverage for these specific opcodes as they tend to appear in later stages - their presence does help in some upcoming patches (e.g. #152107) and I'd prefer to get them committed early.