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Merged
merged 1 commit into from
Aug 28, 2025
Merged

AMDGPU: Add missing verifier tests for load/store AGPR case #155815

merged 1 commit into from
Aug 28, 2025
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@arsenm arsenm commented Aug 28, 2025

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arsenm commented Aug 28, 2025

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@arsenm arsenm marked this pull request as ready for review August 28, 2025 10:45
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llvmbot commented Aug 28, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/155815.diff

1 Files Affected:

  • (added) llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir (+92)
diff --git a/llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir b/llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir
new file mode 100644
index 0000000000000..956a8b80e4082
--- /dev/null
+++ b/llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir
@@ -0,0 +1,92 @@
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=none -filetype=null %s 2>&1 | FileCheck -implicit-check-not=Bad %s
+
+---
+name: invalid_mixed_agpr_vgpr_ops_ds_atomic
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+  %addr:vgpr_32 = IMPLICIT_DEF
+  %vgpr:vgpr_32 = IMPLICIT_DEF
+  %agpr:agpr_32 = IMPLICIT_DEF
+  %a_or_v:av_32 = IMPLICIT_DEF
+
+  ; CHECK: Bad machine code: Invalid register class: vdata and vdst should be both VGPR or AGPR
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %4:agpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %vgpr, %vgpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: Bad machine code: Invalid register class: vdata and vdst should be both VGPR or AGPR
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %5:vgpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %agpr, %vgpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %6:vgpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %vgpr, %agpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %7:av_32 = DS_CMPST_RTN_B32_gfx9 %addr, %vgpr, %vgpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %8:vgpr_32 = DS_CMPST_RTN_B32_gfx9 %vgpr, %a_or_v, %vgpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %9:vgpr_32 = DS_CMPST_RTN_B32_gfx9 %vgpr, %vgpr, %a_or_v, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: vdata and vdst should be both VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %10:av_32 = DS_CMPST_RTN_B32_gfx9 %addr, %agpr, %agpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: vdata and vdst should be both VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %11:agpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %a_or_v, %agpr, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %12:agpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %agpr, %a_or_v, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: vdata and vdst should be both VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %13:agpr_32 = DS_CMPST_RTN_B32_gfx9 %addr, %a_or_v, %a_or_v, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  %14:av_32 = DS_CMPST_RTN_B32_gfx9 %addr, %a_or_v, %a_or_v, 0, 0, implicit $exec :: (load store seq_cst monotonic (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %a_or_v, %a_or_v, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %agpr, %vgpr, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %vgpr, %agpr, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %vgpr, %a_or_v, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %a_or_v, %vgpr, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %agpr, %a_or_v, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+  ; CHECK: *** Bad machine code: Invalid register class: both data operands should be VGPR or AGPR ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  ; CHECK: *** Bad machine code: Illegal virtual register for instruction ***
+  DS_WRITE2_B32_gfx9 %addr, %a_or_v, %agpr, 10, 24, 0, implicit $exec :: (store (s32), addrspace 3), (store (s32), addrspace 3)
+
+...

@arsenm arsenm merged commit f4950f6 into main Aug 28, 2025
13 checks passed
@arsenm arsenm deleted the users/arsenm/amdgpu/add-test-verify-load-store-match-agpr-vgpr branch August 28, 2025 12:23
t-a-james pushed a commit to t-a-james/llvm-project that referenced this pull request Aug 28, 2025
Merge branch 'bugprone-method-hiding' of github.com:t-a-james/llvm-pr…
d13339b 
…oject into bugprone-method-hiding

* 'bugprone-method-hiding' of github.com:t-a-james/llvm-project: (230 commits)
  [SimplifyCFG] Move token type check into canReplaceOperandWithVariable()
  [ADT] Fix signed integer overflow (llvm#155826)
  [Offload] Update LIBOMPTARGET_INFO text for `attach` map-type. (llvm#155509)
  [CMake][AIX] Enable CMP0182: Create shared library archives by default (llvm#155686)
  AMDGPU: Add tests for atomics with AGPR operands (llvm#155820)
  [AArch64] Split zero cycle zeoring per register class (llvm#154561)
  [gn build] Port fa883e1
  [mlir][tosa] Allow shift operand of tosa::MulOp as non-constant (llvm#155197)
  [AArch64][NFC] Add MCInstrAnalysis unittests (llvm#155609)
  [Offload][OpenMP] Tests require libc on GPU for printf (llvm#155785)
  AMDGPU: Add missing verifier tests for load/store AGPR case (llvm#155815)
  [lldb-mcp] Fix building for Windows
  Revert "[lldb] Correct a usage after a rename was merged. (llvm#155720)"
  Revert "[lldb] NFC Moving mcp::Transport into its own file. (llvm#155711)"
  [lldb][test] Run ranges::ref_vew test only for libc++ (llvm#155813)
  [SCCP][FuncSpec] Poison unreachable constant global variable user (llvm#155753)
  [LoongArch] Lowering v32i8 vector mask generation to `VMSKLTZ` (llvm#149953)
  [flang][docs][NFC] Remove stray backtick (llvm#154974)
  [MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in LinalgOps.cpp (NFC)
  [MLIR] Apply clang-tidy fixes for performance-move-const-arg in VariantValue.cpp (NFC)
  ...
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@Pierre-vh Pierre-vh Pierre-vh approved these changes

@cdevadas cdevadas Awaiting requested review from cdevadas

@rampitec rampitec Awaiting requested review from rampitec

@shiltian shiltian Awaiting requested review from shiltian

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