micropython · dpgeorge · Aug 18, 2025 · Aug 19, 2025 · Aug 19, 2025 · Aug 19, 2025
diff --git a/ports/zephyr/CMakeLists.txt b/ports/zephyr/CMakeLists.txt
@@ -30,6 +30,7 @@ project(micropython)
 set(MICROPY_PORT_DIR    ${CMAKE_CURRENT_SOURCE_DIR})
 set(MICROPY_DIR         ${MICROPY_PORT_DIR}/../..)
 set(MICROPY_TARGET      micropython)
+set(MICROPY_BOARD       ${BOARD}) # maybe zephyr_${BOARD} or even uppercase version of that?
 
 include(${MICROPY_DIR}/py/py.cmake)
 include(${MICROPY_DIR}/extmod/extmod.cmake)

diff --git a/tests/extmod/machine_uart_irq_txidle.py b/tests/extmod/machine_uart_irq_txidle.py
@@ -10,32 +10,7 @@
     raise SystemExit
 
 import time, sys
-
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "mimxrt" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "nrf" in sys.platform:
-    uart_id = 0
-    tx_pin = None
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 
 def irq(u):
@@ -46,11 +21,7 @@ def irq(u):
 
 # Test that the IRQ is called after the write has completed.
 for bits_per_s in (2400, 9600, 115200):
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
-
+    uart = UART(*uart_loopback_args, bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_TXIDLE)
 
     # The IRQ_TXIDLE shall trigger after the message has been sent. Thus

diff --git a/tests/extmod/machine_uart_tx.py b/tests/extmod/machine_uart_tx.py
@@ -8,50 +8,40 @@
     raise SystemExit
 
 import time, sys
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 initial_delay_ms = 0
 bit_margin = 0
 timing_margin_us = 100
 
-# Configure pins based on the target.
+# Tune test parameters based on the target.
 if "alif" in sys.platform:
-    uart_id = 1
-    pins = {}
     bit_margin = 1
 elif "esp32" in sys.platform:
-    uart_id = 1
-    pins = {}
     timing_margin_us = 400
 elif "mimxrt" in sys.platform:
-    uart_id = 1
-    pins = {}
     initial_delay_ms = 20  # UART sends idle frame after init, so wait for that
     bit_margin = 1
 elif "pyboard" in sys.platform:
-    if "STM32WB" in sys.implementation._machine:
-        uart_id = "LP1"
-    else:
-        uart_id = 4
-    pins = {}
     initial_delay_ms = 50  # UART sends idle frame after init, so wait for that
     bit_margin = 1  # first start-bit must wait to sync with the UART clock
 elif "rp2" in sys.platform:
-    uart_id = 0
-    pins = {"tx": "GPIO0", "rx": "GPIO1"}
     timing_margin_us = 180
 elif "samd" in sys.platform:
-    uart_id = 2
-    pins = {"tx": "D1", "rx": "D0"}
     timing_margin_us = 300
     bit_margin = 1
-else:
-    print("SKIP")
-    raise SystemExit
 
 # Test that write+flush takes the expected amount of time to execute.
 for bits_per_s in (2400, 9600, 115200):
     text = "Hello World"
-    uart = UART(uart_id, bits_per_s, bits=8, parity=None, stop=1, **pins)
+    uart = UART(
+        *uart_loopback_args,
+        baudrate=bits_per_s,
+        bits=8,
+        parity=None,
+        stop=1,
+        **uart_loopback_kwargs,
+    )
     time.sleep_ms(initial_delay_ms)
 
     start_us = time.ticks_us()

diff --git a/tests/extmod_hardware/machine_uart_irq_break.py b/tests/extmod_hardware/machine_uart_irq_break.py
@@ -12,23 +12,7 @@
     raise SystemExit
 
 import time, sys
-
-# Configure pins based on the target.
-if "esp32" in sys.platform:
-    _machine = sys.implementation._machine
-    if "ESP32S2" in _machine or "ESP32C3" in _machine or "ESP32C6" in _machine:
-        print("SKIP")
-        raise SystemExit
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 
 def irq(u):
@@ -37,7 +21,7 @@ def irq(u):
 
 # Test that the IRQ is called for each break received.
 for bits_per_s in (2400, 9600, 57600):
-    uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_BREAK)
 
     print("write", bits_per_s)

diff --git a/tests/extmod_hardware/machine_uart_irq_rx.py b/tests/extmod_hardware/machine_uart_irq_rx.py
@@ -13,49 +13,14 @@
 
 import time, sys
 
-byte_by_byte = False
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-    rx_pin = None
-elif "esp32" in sys.platform:
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "pyboard" in sys.platform:
-    if "STM32WB" in sys.implementation._machine:
-        # LPUART(1) is on PA2/PA3
-        uart_id = "LP1"
-    else:
-        # UART(4) is on PA0/PA1
-        uart_id = 4
-    tx_pin = None
-    rx_pin = None
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-    byte_by_byte = True
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "nrf" in sys.platform:
-    uart_id = 0
-    tx_pin = None
-    rx_pin = None
-elif "renesas-ra" in sys.platform:
-    uart_id = 9
-    tx_pin = None  # P602 @ RA6M2
-    rx_pin = None  # P601 @ RA6M2
-elif "CC3200" in sys.implementation._machine:
+if "CC3200" in sys.implementation._machine:
     # CC3200 doesn't work because it's too slow and has an allocation error in the handler.
     print("SKIP")
     raise SystemExit
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
+
+byte_by_byte = "ItsyBitsy M0" in sys.implementation._machine
 
 
 def irq(u):
@@ -67,11 +32,7 @@ def irq(u):
 # Test that the IRQ is called for each byte received.
 # Use slow baudrates so that the IRQ has time to run.
 for bits_per_s in (2400, 9600):
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
-
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_RX)
 
     print("write", bits_per_s)

diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -12,52 +12,10 @@
     raise SystemExit
 
 import time, sys
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 # Target tuning options.
-tune_wait_initial_rxidle = False
-
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-    rx_pin = None
-elif "esp32" in sys.platform:
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "mimxrt" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "pyboard" in sys.platform:
-    tune_wait_initial_rxidle = True
-    if "STM32WB" in sys.implementation._machine:
-        # LPUART(1) is on PA2/PA3
-        uart_id = "LP1"
-    else:
-        # UART(4) is on PA0/PA1
-        uart_id = 4
-    tx_pin = None
-    rx_pin = None
-elif "renesas-ra" in sys.platform:
-    uart_id = 9
-    tx_pin = None  # P602 @ RA6M2
-    rx_pin = None  # P601 @ RA6M2
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-    byte_by_byte = True
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+tune_wait_initial_rxidle = sys.platform == "pyboard"
 
 
 def irq(u):
@@ -71,10 +29,7 @@ def irq(u):
     print("========")
     print("bits_per_s:", bits_per_s)
 
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
 
     # Ignore a possible initial RXIDLE condition after creating UART.
     if tune_wait_initial_rxidle:

diff --git a/tests/feature_check/target_info.py b/tests/feature_check/target_info.py
@@ -20,6 +20,7 @@
     "xtensawin",
     "rv32imc",
 ][sys_mpy >> 10]
+build = getattr(sys.implementation, "_build", "unknown")
 thread = getattr(sys.implementation, "_thread", None)
 
 # Detect how many bits of precision the floating point implementation has.
@@ -33,4 +34,4 @@
 except NameError:
     float_prec = 0
 
-print(platform, arch, thread, float_prec, len("α") == 1)
+print(platform, arch, build, thread, float_prec, len("α") == 1)