ZJIT: Make sure output operands are not VRegs #14188
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❌ Tests Failed✖️no tests failed ✔️62274 tests passed(2 flakes) |
k0kubun
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Aug 13, 2025
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Make LIR SSA.
I mean this PR doesn't because there's still load_into that allows writes to VReg, but we do write to VReg using load_into for , so I agree we should merge this first and then work on load_into separately if we want to.
Huh. We return Opnd::Reg from param_opnd and we load_into that register, and VReg is only used by its wrapper gen_param. So I guess we can ban VReg from load_into now?
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I just updated the comment ^. I think we can do: pub fn load_into(&mut self, dest: Opnd, opnd: Opnd) {
- assert!(matches!(dest, Opnd::Reg(_) | Opnd::VReg{..}), "Destination of load_into must be a register");
+ assert!(matches!(dest, Opnd::Reg(_)), "Destination of load_into must be a register, got: {dest:?}"); as well. |
st0012
approved these changes
Aug 13, 2025
k0kubun
reviewed
Aug 13, 2025
k0kubun
approved these changes
Aug 13, 2025
Make LIR SSA.
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Make LIR SSA.