Papers by C. Selvanayagam
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011
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IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011
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IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011
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2009 11th Electronics Packaging Technology Conference, 2009
ABSTRACT With the most popular electronics products being the slimmest ones with the highest func... more ABSTRACT With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5Ã10-6/°C) and silicon (2.5Ã10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.
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2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008
This paper presents a study of the resistance of solder joints to failure when subjected to strai... more This paper presents a study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop impact on a portable electronic product. Two test methods are used in this study: board-level drop/shock test (BLDT) and component-level ball impact test (BIT). The performance of 12 material combinations consisting of 6 solder alloys and 2 pad finishes were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristics, namely, number of drops to failure for BLDT and peak load, total fracture energy, and energy to peak load for BIT, were evaluated. Analysis of the test results indicates that there is a lack of universal correlation between BLDT and BIT. Nevertheless, BIT can still serve as a test methodology for quality assurance in view of the strong correlation between the measured BIT characteristics and the failure mode. The total fracture energy parameter is preferred over the peak load and energy to peak load due to its higher sensitivity and reduced susceptibility to measurement error.
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2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012
ABSTRACT
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Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of d... more Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of drop impact conditions. This study presents an experimental procedure for obtaining the material properties of solder alloys at these medium strain rates. The effect of grain size on the medium strain rate behavior of solder alloys is also studied, using SnPb alloy as an example. Grain
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Microelectronics Reliability, 2008
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Journal of Electronic Materials, 2008
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IEEE Transactions on Electronics Packaging Manufacturing, 2000
The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impac... more The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a
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IEEE Transactions on Advanced Packaging, 2000
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2009 59th Electronic Components and Technology Conference, 2009
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Papers by C. Selvanayagam