16#include "clang/AST/Attrs.inc"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/TargetParser/RISCVISAInfo.h"
31#include "llvm/TargetParser/RISCVTargetParser.h"
45struct RVVIntrinsicDef {
47 std::string BuiltinName;
50 StringRef RequiredExtensions;
56struct RVVOverloadIntrinsicDef {
64#define DECL_SIGNATURE_TABLE
65#include "clang/Basic/riscv_vector_builtin_sema.inc"
66#undef DECL_SIGNATURE_TABLE
70#define DECL_SIGNATURE_TABLE
71#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"
72#undef DECL_SIGNATURE_TABLE
76#define DECL_SIGNATURE_TABLE
77#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"
78#undef DECL_SIGNATURE_TABLE
82#define DECL_INTRINSIC_RECORDS
83#include "clang/Basic/riscv_vector_builtin_sema.inc"
84#undef DECL_INTRINSIC_RECORDS
88#define DECL_INTRINSIC_RECORDS
89#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"
90#undef DECL_INTRINSIC_RECORDS
94#define DECL_INTRINSIC_RECORDS
95#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"
96#undef DECL_INTRINSIC_RECORDS
103 case IntrinsicKind::RVV:
105 case IntrinsicKind::SIFIVE_VECTOR:
107 case IntrinsicKind::ANDES_VECTOR:
110 llvm_unreachable(
"Unhandled IntrinsicKind");
115 switch (
Type->getScalarType()) {
116 case ScalarTypeKind::Void:
119 case ScalarTypeKind::Size_t:
122 case ScalarTypeKind::Ptrdiff_t:
125 case ScalarTypeKind::UnsignedLong:
128 case ScalarTypeKind::SignedLong:
131 case ScalarTypeKind::Boolean:
134 case ScalarTypeKind::SignedInteger:
137 case ScalarTypeKind::UnsignedInteger:
140 case ScalarTypeKind::BFloat:
143 case ScalarTypeKind::Float:
144 switch (
Type->getElementBitwidth()) {
155 llvm_unreachable(
"Unsupported floating point width.");
160 llvm_unreachable(
"Unhandled type.");
162 if (
Type->isVector()) {
169 if (
Type->isConstant())
173 if (
Type->isPointer())
184 bool ConstructedRISCVVBuiltins;
185 bool ConstructedRISCVSiFiveVectorBuiltins;
186 bool ConstructedRISCVAndesVectorBuiltins;
189 std::vector<RVVIntrinsicDef> IntrinsicList;
191 StringMap<uint32_t> Intrinsics;
193 StringMap<RVVOverloadIntrinsicDef> OverloadIntrinsics;
197 StringRef OverloadedSuffixStr,
bool IsMask,
210 ConstructedRISCVVBuiltins =
false;
211 ConstructedRISCVSiFiveVectorBuiltins =
false;
212 ConstructedRISCVAndesVectorBuiltins =
false;
225void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
229 for (
auto &
Record : Recs) {
237 K,
Record.OverloadedSuffixIndex,
Record.OverloadedSuffixSize);
244 const Policy DefaultPolicy;
248 BasicProtoSeq,
false,
250 UnMaskedPolicyScheme, DefaultPolicy,
Record.IsTuple);
255 BasicProtoSeq,
true,
Record.HasMaskedOffOperand,
256 Record.HasVL,
Record.NF, MaskedPolicyScheme, DefaultPolicy,
259 bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
260 bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
267 for (
unsigned int TypeRangeMaskShift = 0;
268 TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);
269 ++TypeRangeMaskShift) {
270 unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
271 BaseType =
static_cast<BasicType>(BaseTypeI);
273 if ((BaseTypeI &
Record.TypeRangeMask) != BaseTypeI)
277 for (
int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
278 if (!(
Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
281 std::optional<RVVTypes> Types =
282 TypeCache.computeTypes(BaseType, Log2LMUL,
Record.NF, ProtoSeq);
285 if (!Types.has_value())
289 TypeCache, BaseType, Log2LMUL, SuffixProto);
291 TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto);
294 InitRVVIntrinsic(
Record, SuffixStr, OverloadedSuffixStr,
false, *Types,
295 UnMaskedHasPolicy, DefaultPolicy);
298 if (
Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) {
299 for (
auto P : SupportedUnMaskedPolicies) {
302 BasicProtoSeq,
false,
304 UnMaskedPolicyScheme,
P,
Record.IsTuple);
305 std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
306 BaseType, Log2LMUL,
Record.NF, PolicyPrototype);
307 InitRVVIntrinsic(
Record, SuffixStr, OverloadedSuffixStr,
308 false, *PolicyTypes, UnMaskedHasPolicy,
315 std::optional<RVVTypes> MaskTypes =
316 TypeCache.computeTypes(BaseType, Log2LMUL,
Record.NF, ProtoMaskSeq);
317 InitRVVIntrinsic(
Record, SuffixStr, OverloadedSuffixStr,
true,
318 *MaskTypes, MaskedHasPolicy, DefaultPolicy);
319 if (
Record.MaskedPolicyScheme == PolicyScheme::SchemeNone)
322 for (
auto P : SupportedMaskedPolicies) {
325 BasicProtoSeq,
true,
Record.HasMaskedOffOperand,
328 std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
329 BaseType, Log2LMUL,
Record.NF, PolicyPrototype);
330 InitRVVIntrinsic(
Record, SuffixStr, OverloadedSuffixStr,
331 true, *PolicyTypes, MaskedHasPolicy,
P);
338void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
341 ConstructedRISCVVBuiltins =
true;
345 !ConstructedRISCVSiFiveVectorBuiltins) {
346 ConstructedRISCVSiFiveVectorBuiltins =
true;
348 IntrinsicKind::SIFIVE_VECTOR);
351 !ConstructedRISCVAndesVectorBuiltins) {
352 ConstructedRISCVAndesVectorBuiltins =
true;
354 IntrinsicKind::ANDES_VECTOR);
359void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
361 StringRef OverloadedSuffixStr,
bool IsMasked,
RVVTypes &Signature,
362 bool HasPolicy,
Policy PolicyAttrs) {
364 std::string Name =
Record.Name;
365 if (!SuffixStr.empty())
366 Name +=
"_" + SuffixStr.str();
369 std::string OverloadedName;
370 if (!
Record.OverloadedName)
371 OverloadedName = StringRef(
Record.Name).split(
"_").first.str();
373 OverloadedName =
Record.OverloadedName;
374 if (!OverloadedSuffixStr.empty())
375 OverloadedName +=
"_" + OverloadedSuffixStr.str();
378 std::string BuiltinName = std::string(
Record.Name);
381 OverloadedName, PolicyAttrs,
382 Record.HasFRMRoundModeOp);
385 uint32_t Index = IntrinsicList.size();
386 assert(IntrinsicList.size() == (
size_t)Index &&
387 "Intrinsics indices overflow.");
388 IntrinsicList.push_back({BuiltinName,
Record.RequiredExtensions, Signature});
391 Intrinsics.insert({Name, Index});
394 RVVOverloadIntrinsicDef &OverloadIntrinsicDef =
395 OverloadIntrinsics[OverloadedName];
398 OverloadIntrinsicDef.Indexes.push_back(Index);
401void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(
LookupResult &LR,
407 RVVIntrinsicDef &IDef = IntrinsicList[Index];
409 size_t SigLength = Sigs.size();
416 for (
size_t i = 1; i < SigLength; ++i)
429 Context,
Parent,
Loc,
Loc, II, BuiltinFuncType,
nullptr,
436 const auto *FP = cast<FunctionProtoType>(BuiltinFuncType);
438 for (
unsigned IParm = 0,
E = FP->getNumParams(); IParm !=
E; ++IParm) {
441 FP->getParamType(IParm),
nullptr,
SC_None,
nullptr);
443 ParmList.push_back(Parm);
445 RVVIntrinsicDecl->setParams(ParmList);
449 RVVIntrinsicDecl->
addAttr(OverloadableAttr::CreateImplicit(Context));
451 if (IDef.RequiredExtensions !=
"")
453 TargetAttr::CreateImplicit(Context, IDef.RequiredExtensions));
458 BuiltinAliasAttr::CreateImplicit(S.
Context, &IntrinsicII));
464bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(
LookupResult &LR,
467 StringRef Name = II->
getName();
468 if (!Name.consume_front(
"__riscv_"))
472 auto OvIItr = OverloadIntrinsics.find(Name);
473 if (OvIItr != OverloadIntrinsics.end()) {
474 const RVVOverloadIntrinsicDef &OvIntrinsicDef = OvIItr->second;
475 for (
auto Index : OvIntrinsicDef.Indexes)
476 CreateRVVIntrinsicDecl(LR, II, PP, Index,
485 auto Itr = Intrinsics.find(Name);
486 if (Itr != Intrinsics.end()) {
487 CreateRVVIntrinsicDecl(LR, II, PP, Itr->second,
497std::unique_ptr<clang::sema::RISCVIntrinsicManager>
499 return std::make_unique<RISCVIntrinsicManagerImpl>(S);
514 int64_t Val =
Result.getSExtValue();
515 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7))
518 return Diag(TheCall->
getBeginLoc(), diag::err_riscv_builtin_invalid_lmul)
523 llvm::StringMap<bool> &FunctionFeatureMap,
526 assert((EGW == 128 || EGW == 256) &&
"EGW can only be 128 or 256 bits");
532 unsigned MinElemCount = Info.
EC.getKnownMinValue();
534 unsigned EGS = EGW / ElemSize;
537 if (EGS <= MinElemCount)
541 assert(EGS % MinElemCount == 0);
542 unsigned VScaleFactor = EGS / MinElemCount;
544 unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;
545 std::string RequiredExt =
"zvl" + std::to_string(MinRequiredVLEN) +
"b";
546 if (!TI.
hasFeature(RequiredExt) && !FunctionFeatureMap.lookup(RequiredExt))
548 diag::err_riscv_type_requires_extension)
549 <<
Type << RequiredExt;
559 llvm::StringMap<bool> FunctionFeatureMap;
563 StringRef FeaturesStr = A->getFeaturesStr();
565 FeaturesStr.split(RequiredFeatures,
',');
566 for (
auto RF : RequiredFeatures)
567 if (!TI.
hasFeature(RF) && !FunctionFeatureMap.lookup(RF))
569 diag::err_riscv_builtin_requires_extension)
578 case RISCVVector::BI__builtin_rvv_vmulhsu_vv:
579 case RISCVVector::BI__builtin_rvv_vmulhsu_vx:
580 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tu:
581 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tu:
582 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_m:
583 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_m:
584 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_mu:
585 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_mu:
586 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tum:
587 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tum:
588 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tumu:
589 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tumu:
590 case RISCVVector::BI__builtin_rvv_vmulhu_vv:
591 case RISCVVector::BI__builtin_rvv_vmulhu_vx:
592 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tu:
593 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tu:
594 case RISCVVector::BI__builtin_rvv_vmulhu_vv_m:
595 case RISCVVector::BI__builtin_rvv_vmulhu_vx_m:
596 case RISCVVector::BI__builtin_rvv_vmulhu_vv_mu:
597 case RISCVVector::BI__builtin_rvv_vmulhu_vx_mu:
598 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tum:
599 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tum:
600 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tumu:
601 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tumu:
602 case RISCVVector::BI__builtin_rvv_vmulh_vv:
603 case RISCVVector::BI__builtin_rvv_vmulh_vx:
604 case RISCVVector::BI__builtin_rvv_vmulh_vv_tu:
605 case RISCVVector::BI__builtin_rvv_vmulh_vx_tu:
606 case RISCVVector::BI__builtin_rvv_vmulh_vv_m:
607 case RISCVVector::BI__builtin_rvv_vmulh_vx_m:
608 case RISCVVector::BI__builtin_rvv_vmulh_vv_mu:
609 case RISCVVector::BI__builtin_rvv_vmulh_vx_mu:
610 case RISCVVector::BI__builtin_rvv_vmulh_vv_tum:
611 case RISCVVector::BI__builtin_rvv_vmulh_vx_tum:
612 case RISCVVector::BI__builtin_rvv_vmulh_vv_tumu:
613 case RISCVVector::BI__builtin_rvv_vmulh_vx_tumu:
614 case RISCVVector::BI__builtin_rvv_vsmul_vv:
615 case RISCVVector::BI__builtin_rvv_vsmul_vx:
616 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:
617 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:
618 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:
619 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:
620 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:
621 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:
622 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:
623 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:
624 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:
625 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {
630 !FunctionFeatureMap.lookup(
"v"))
632 diag::err_riscv_builtin_requires_extension)
639 auto CheckVSetVL = [&](
unsigned SEWOffset,
unsigned LMULOffset) ->
bool {
641 llvm::StringMap<bool> FunctionFeatureMap;
643 llvm::APSInt SEWResult;
644 llvm::APSInt LMULResult;
648 int SEWValue = SEWResult.getSExtValue();
649 int LMULValue = LMULResult.getSExtValue();
650 if (((SEWValue == 0 && LMULValue == 5) ||
651 (SEWValue == 1 && LMULValue == 6) ||
652 (SEWValue == 2 && LMULValue == 7) ||
655 !FunctionFeatureMap.lookup(
"zve64x"))
657 diag::err_riscv_builtin_requires_extension)
663 case RISCVVector::BI__builtin_rvv_vsetvli:
664 return CheckVSetVL(1, 2);
665 case RISCVVector::BI__builtin_rvv_vsetvlimax:
666 return CheckVSetVL(0, 1);
667 case RISCVVector::BI__builtin_rvv_vget_v: {
678 MaxIndex = (VecInfo.
EC.getKnownMinValue() * VecInfo.
NumVectors) /
679 (ResVecInfo.
EC.getKnownMinValue() * ResVecInfo.
NumVectors);
682 case RISCVVector::BI__builtin_rvv_vset_v: {
693 MaxIndex = (ResVecInfo.
EC.getKnownMinValue() * ResVecInfo.
NumVectors) /
698 case RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu:
699 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:
700 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:
701 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {
710 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:
711 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {
717 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:
718 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {
724 case RISCVVector::BI__builtin_rvv_vaesdf_vv:
725 case RISCVVector::BI__builtin_rvv_vaesdf_vs:
726 case RISCVVector::BI__builtin_rvv_vaesdm_vv:
727 case RISCVVector::BI__builtin_rvv_vaesdm_vs:
728 case RISCVVector::BI__builtin_rvv_vaesef_vv:
729 case RISCVVector::BI__builtin_rvv_vaesef_vs:
730 case RISCVVector::BI__builtin_rvv_vaesem_vv:
731 case RISCVVector::BI__builtin_rvv_vaesem_vs:
732 case RISCVVector::BI__builtin_rvv_vaesz_vs:
733 case RISCVVector::BI__builtin_rvv_vsm4r_vv:
734 case RISCVVector::BI__builtin_rvv_vsm4r_vs:
735 case RISCVVector::BI__builtin_rvv_vaesdf_vv_tu:
736 case RISCVVector::BI__builtin_rvv_vaesdf_vs_tu:
737 case RISCVVector::BI__builtin_rvv_vaesdm_vv_tu:
738 case RISCVVector::BI__builtin_rvv_vaesdm_vs_tu:
739 case RISCVVector::BI__builtin_rvv_vaesef_vv_tu:
740 case RISCVVector::BI__builtin_rvv_vaesef_vs_tu:
741 case RISCVVector::BI__builtin_rvv_vaesem_vv_tu:
742 case RISCVVector::BI__builtin_rvv_vaesem_vs_tu:
743 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:
744 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:
745 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {
753 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:
754 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:
755 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:
756 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:
757 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:
758 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {
765 if (ElemSize == 64 && !TI.
hasFeature(
"zvknhb") &&
766 !FunctionFeatureMap.lookup(
"zvknhb"))
768 diag::err_riscv_builtin_requires_extension)
771 if (!TI.
hasFeature(
"zvknha") && !FunctionFeatureMap.lookup(
"zvknha") &&
772 !TI.
hasFeature(
"zvknhb") && !FunctionFeatureMap.lookup(
"zvknhb"))
774 diag::err_riscv_builtin_requires_extension)
776 <<
"zvknha or zvknhb";
779 Arg0Type, ElemSize * 4) ||
781 Arg1Type, ElemSize * 4) ||
783 Arg2Type, ElemSize * 4);
786 case RISCVVector::BI__builtin_rvv_sf_vc_i_se:
793 case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:
798 case RISCVVector::BI__builtin_rvv_sf_vc_v_i:
799 case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:
804 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv:
805 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:
809 case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:
810 case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:
811 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:
812 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:
813 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:
814 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:
818 case RISCVVector::BI__builtin_rvv_sf_vc_x_se:
824 case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:
825 case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:
827 case RISCVVector::BI__builtin_rvv_sf_vc_v_x:
828 case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:
832 case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:
833 case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:
834 case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:
835 case RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:
837 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv:
838 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv:
839 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:
840 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:
842 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:
843 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:
844 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:
845 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:
846 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:
847 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:
848 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:
849 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:
852 case RISCVVector::BI__builtin_rvv_sf_vc_fv_se:
856 case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:
857 case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:
858 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:
859 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:
860 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:
861 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:
863 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv:
864 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:
868 case RISCV::BI__builtin_riscv_aes32dsi:
869 case RISCV::BI__builtin_riscv_aes32dsmi:
870 case RISCV::BI__builtin_riscv_aes32esi:
871 case RISCV::BI__builtin_riscv_aes32esmi:
872 case RISCV::BI__builtin_riscv_sm4ks:
873 case RISCV::BI__builtin_riscv_sm4ed:
876 case RISCV::BI__builtin_riscv_aes64ks1i:
879 case RISCVVector::BI__builtin_rvv_vaaddu_vv:
880 case RISCVVector::BI__builtin_rvv_vaaddu_vx:
881 case RISCVVector::BI__builtin_rvv_vaadd_vv:
882 case RISCVVector::BI__builtin_rvv_vaadd_vx:
883 case RISCVVector::BI__builtin_rvv_vasubu_vv:
884 case RISCVVector::BI__builtin_rvv_vasubu_vx:
885 case RISCVVector::BI__builtin_rvv_vasub_vv:
886 case RISCVVector::BI__builtin_rvv_vasub_vx:
887 case RISCVVector::BI__builtin_rvv_vsmul_vv:
888 case RISCVVector::BI__builtin_rvv_vsmul_vx:
889 case RISCVVector::BI__builtin_rvv_vssra_vv:
890 case RISCVVector::BI__builtin_rvv_vssra_vx:
891 case RISCVVector::BI__builtin_rvv_vssrl_vv:
892 case RISCVVector::BI__builtin_rvv_vssrl_vx:
893 case RISCVVector::BI__builtin_rvv_vnclip_wv:
894 case RISCVVector::BI__builtin_rvv_vnclip_wx:
895 case RISCVVector::BI__builtin_rvv_vnclipu_wv:
896 case RISCVVector::BI__builtin_rvv_vnclipu_wx:
898 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu:
899 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu:
900 case RISCVVector::BI__builtin_rvv_vaadd_vv_tu:
901 case RISCVVector::BI__builtin_rvv_vaadd_vx_tu:
902 case RISCVVector::BI__builtin_rvv_vasubu_vv_tu:
903 case RISCVVector::BI__builtin_rvv_vasubu_vx_tu:
904 case RISCVVector::BI__builtin_rvv_vasub_vv_tu:
905 case RISCVVector::BI__builtin_rvv_vasub_vx_tu:
906 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:
907 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:
908 case RISCVVector::BI__builtin_rvv_vssra_vv_tu:
909 case RISCVVector::BI__builtin_rvv_vssra_vx_tu:
910 case RISCVVector::BI__builtin_rvv_vssrl_vv_tu:
911 case RISCVVector::BI__builtin_rvv_vssrl_vx_tu:
912 case RISCVVector::BI__builtin_rvv_vnclip_wv_tu:
913 case RISCVVector::BI__builtin_rvv_vnclip_wx_tu:
914 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:
915 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:
916 case RISCVVector::BI__builtin_rvv_vaaddu_vv_m:
917 case RISCVVector::BI__builtin_rvv_vaaddu_vx_m:
918 case RISCVVector::BI__builtin_rvv_vaadd_vv_m:
919 case RISCVVector::BI__builtin_rvv_vaadd_vx_m:
920 case RISCVVector::BI__builtin_rvv_vasubu_vv_m:
921 case RISCVVector::BI__builtin_rvv_vasubu_vx_m:
922 case RISCVVector::BI__builtin_rvv_vasub_vv_m:
923 case RISCVVector::BI__builtin_rvv_vasub_vx_m:
924 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:
925 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:
926 case RISCVVector::BI__builtin_rvv_vssra_vv_m:
927 case RISCVVector::BI__builtin_rvv_vssra_vx_m:
928 case RISCVVector::BI__builtin_rvv_vssrl_vv_m:
929 case RISCVVector::BI__builtin_rvv_vssrl_vx_m:
930 case RISCVVector::BI__builtin_rvv_vnclip_wv_m:
931 case RISCVVector::BI__builtin_rvv_vnclip_wx_m:
932 case RISCVVector::BI__builtin_rvv_vnclipu_wv_m:
933 case RISCVVector::BI__builtin_rvv_vnclipu_wx_m:
935 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:
936 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:
937 case RISCVVector::BI__builtin_rvv_vaaddu_vv_mu:
938 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tum:
939 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tumu:
940 case RISCVVector::BI__builtin_rvv_vaaddu_vx_mu:
941 case RISCVVector::BI__builtin_rvv_vaadd_vv_tum:
942 case RISCVVector::BI__builtin_rvv_vaadd_vv_tumu:
943 case RISCVVector::BI__builtin_rvv_vaadd_vv_mu:
944 case RISCVVector::BI__builtin_rvv_vaadd_vx_tum:
945 case RISCVVector::BI__builtin_rvv_vaadd_vx_tumu:
946 case RISCVVector::BI__builtin_rvv_vaadd_vx_mu:
947 case RISCVVector::BI__builtin_rvv_vasubu_vv_tum:
948 case RISCVVector::BI__builtin_rvv_vasubu_vv_tumu:
949 case RISCVVector::BI__builtin_rvv_vasubu_vv_mu:
950 case RISCVVector::BI__builtin_rvv_vasubu_vx_tum:
951 case RISCVVector::BI__builtin_rvv_vasubu_vx_tumu:
952 case RISCVVector::BI__builtin_rvv_vasubu_vx_mu:
953 case RISCVVector::BI__builtin_rvv_vasub_vv_tum:
954 case RISCVVector::BI__builtin_rvv_vasub_vv_tumu:
955 case RISCVVector::BI__builtin_rvv_vasub_vv_mu:
956 case RISCVVector::BI__builtin_rvv_vasub_vx_tum:
957 case RISCVVector::BI__builtin_rvv_vasub_vx_tumu:
958 case RISCVVector::BI__builtin_rvv_vasub_vx_mu:
959 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:
960 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:
961 case RISCVVector::BI__builtin_rvv_vssra_vv_mu:
962 case RISCVVector::BI__builtin_rvv_vssra_vx_mu:
963 case RISCVVector::BI__builtin_rvv_vssrl_vv_mu:
964 case RISCVVector::BI__builtin_rvv_vssrl_vx_mu:
965 case RISCVVector::BI__builtin_rvv_vnclip_wv_mu:
966 case RISCVVector::BI__builtin_rvv_vnclip_wx_mu:
967 case RISCVVector::BI__builtin_rvv_vnclipu_wv_mu:
968 case RISCVVector::BI__builtin_rvv_vnclipu_wx_mu:
969 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:
970 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:
971 case RISCVVector::BI__builtin_rvv_vssra_vv_tum:
972 case RISCVVector::BI__builtin_rvv_vssra_vx_tum:
973 case RISCVVector::BI__builtin_rvv_vssrl_vv_tum:
974 case RISCVVector::BI__builtin_rvv_vssrl_vx_tum:
975 case RISCVVector::BI__builtin_rvv_vnclip_wv_tum:
976 case RISCVVector::BI__builtin_rvv_vnclip_wx_tum:
977 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tum:
978 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tum:
979 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:
980 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu:
981 case RISCVVector::BI__builtin_rvv_vssra_vv_tumu:
982 case RISCVVector::BI__builtin_rvv_vssra_vx_tumu:
983 case RISCVVector::BI__builtin_rvv_vssrl_vv_tumu:
984 case RISCVVector::BI__builtin_rvv_vssrl_vx_tumu:
985 case RISCVVector::BI__builtin_rvv_vnclip_wv_tumu:
986 case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu:
987 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu:
988 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu:
990 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm:
991 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm:
992 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm:
993 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm:
994 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm:
995 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm:
996 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm:
997 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm:
998 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm:
999 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm:
1000 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:
1001 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:
1002 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:
1003 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm:
1005 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:
1006 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:
1007 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm:
1008 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm:
1009 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:
1010 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm:
1011 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm:
1012 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm:
1013 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm:
1014 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm:
1015 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm:
1016 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm:
1017 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm:
1018 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm:
1019 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm:
1020 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm:
1021 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm:
1022 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:
1023 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:
1024 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:
1025 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:
1026 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:
1027 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:
1028 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:
1029 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:
1030 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:
1031 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:
1032 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tu:
1033 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tu:
1034 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tu:
1035 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tu:
1036 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tu:
1037 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tu:
1038 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tu:
1039 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:
1040 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:
1041 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:
1042 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tu:
1043 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:
1044 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:
1045 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:
1046 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_m:
1047 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_m:
1048 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_m:
1049 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_m:
1050 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_m:
1051 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_m:
1052 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_m:
1053 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:
1054 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:
1055 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:
1056 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m:
1058 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:
1059 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
1060 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:
1061 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:
1062 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:
1063 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tu:
1064 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tu:
1065 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tu:
1066 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tu:
1067 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tu:
1068 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tu:
1069 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tu:
1070 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:
1071 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:
1072 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:
1073 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:
1074 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:
1075 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:
1076 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:
1077 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:
1078 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:
1079 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:
1080 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:
1081 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:
1082 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:
1083 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:
1084 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:
1085 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:
1086 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:
1087 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:
1088 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:
1089 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:
1090 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:
1091 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:
1092 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:
1093 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:
1094 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:
1095 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:
1096 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:
1097 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:
1098 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm:
1099 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm:
1100 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm:
1101 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm:
1102 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm:
1103 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:
1104 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:
1105 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:
1106 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm:
1107 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm:
1108 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:
1109 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:
1110 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:
1111 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:
1112 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:
1113 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:
1114 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:
1115 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:
1116 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:
1117 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:
1118 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:
1119 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:
1120 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:
1121 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:
1122 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:
1123 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:
1124 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tu:
1125 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tu:
1126 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tu:
1127 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tu:
1128 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tu:
1129 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:
1130 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:
1131 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:
1132 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu:
1133 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu:
1134 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:
1135 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:
1136 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:
1137 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_m:
1138 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_m:
1139 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_m:
1140 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_m:
1141 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_m:
1142 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_m:
1143 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_m:
1144 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_m:
1145 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_m:
1146 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_m:
1147 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_m:
1148 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_m:
1149 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_m:
1150 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_m:
1151 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_m:
1152 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_m:
1153 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_m:
1154 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_m:
1155 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_m:
1156 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_m:
1157 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_m:
1158 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:
1159 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:
1160 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:
1161 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tum:
1162 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tum:
1163 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tum:
1164 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tum:
1165 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tum:
1166 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tum:
1167 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tum:
1168 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:
1169 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:
1170 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:
1171 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tum:
1172 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:
1173 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:
1174 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:
1175 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tumu:
1176 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tumu:
1177 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tumu:
1178 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tumu:
1179 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tumu:
1180 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tumu:
1181 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tumu:
1182 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:
1183 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:
1184 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:
1185 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tumu:
1186 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:
1187 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:
1188 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:
1189 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_mu:
1190 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_mu:
1191 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_mu:
1192 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_mu:
1193 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_mu:
1194 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_mu:
1195 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_mu:
1196 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:
1197 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:
1198 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:
1199 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu:
1201 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:
1202 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:
1203 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m:
1204 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_m:
1205 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_m:
1206 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_m:
1207 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_m:
1208 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_m:
1209 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_m:
1210 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_m:
1211 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_m:
1212 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_m:
1213 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_m:
1214 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_m:
1215 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_m:
1216 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_m:
1217 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_m:
1218 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_m:
1219 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_m:
1220 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_m:
1221 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_m:
1222 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:
1223 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:
1224 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:
1225 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_m:
1226 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_m:
1227 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
1228 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
1229 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
1230 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:
1231 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:
1232 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:
1233 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:
1234 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:
1235 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:
1236 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:
1237 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:
1238 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:
1239 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:
1240 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:
1241 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:
1242 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:
1243 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:
1244 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:
1245 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:
1246 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:
1247 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:
1248 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:
1249 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:
1250 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:
1251 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:
1252 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:
1253 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:
1254 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:
1255 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:
1256 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:
1257 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:
1258 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:
1259 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:
1260 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:
1261 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:
1262 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:
1263 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tum:
1264 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tum:
1265 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tum:
1266 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tum:
1267 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tum:
1268 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:
1269 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:
1270 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:
1271 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tum:
1272 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tum:
1273 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:
1274 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:
1275 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:
1276 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:
1277 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:
1278 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:
1279 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:
1280 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:
1281 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:
1282 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:
1283 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:
1284 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:
1285 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:
1286 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:
1287 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:
1288 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:
1289 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:
1290 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:
1291 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:
1292 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:
1293 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:
1294 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:
1295 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:
1296 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:
1297 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:
1298 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:
1299 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:
1300 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:
1301 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:
1302 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:
1303 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:
1304 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:
1305 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:
1306 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:
1307 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:
1308 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:
1309 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:
1310 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:
1311 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:
1312 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:
1313 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tumu:
1314 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tumu:
1315 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tumu:
1316 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tumu:
1317 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tumu:
1318 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:
1319 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:
1320 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:
1321 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu:
1322 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu:
1323 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
1324 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
1325 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
1326 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:
1327 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:
1328 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:
1329 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:
1330 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:
1331 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:
1332 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:
1333 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:
1334 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:
1335 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:
1336 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:
1337 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:
1338 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:
1339 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:
1340 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:
1341 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:
1342 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:
1343 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:
1344 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:
1345 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:
1346 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:
1347 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:
1348 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:
1349 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:
1350 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:
1351 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:
1352 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:
1353 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:
1354 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:
1355 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:
1356 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:
1357 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:
1358 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:
1359 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_mu:
1360 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_mu:
1361 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_mu:
1362 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_mu:
1363 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_mu:
1364 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:
1365 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:
1366 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
1367 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu:
1368 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu:
1370 case RISCV::BI__builtin_riscv_ntl_load:
1371 case RISCV::BI__builtin_riscv_ntl_store:
1374 assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||
1375 BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&
1376 "Unexpected RISC-V nontemporal load/store builtin!");
1377 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;
1378 unsigned NumArgs = IsStore ? 3 : 2;
1398 PointerArg = PointerArgResult.
get();
1402 Diag(DRE->
getBeginLoc(), diag::err_nontemporal_builtin_must_be_pointer)
1413 diag::err_nontemporal_builtin_must_be_pointer_intfltptr_or_vector)
1425 Context, ValType,
false);
1440 const llvm::StringMap<bool> &FeatureMap) {
1444 unsigned MinElts = Info.
EC.getKnownMinValue();
1447 !FeatureMap.lookup(
"zve64d"))
1448 Diag(
Loc, diag::err_riscv_type_requires_extension,
D) << Ty <<
"zve64d";
1453 !FeatureMap.lookup(
"zve64x"))
1454 Diag(
Loc, diag::err_riscv_type_requires_extension,
D) << Ty <<
"zve64x";
1456 !FeatureMap.lookup(
"zvfhmin") &&
1457 !FeatureMap.lookup(
"xandesvpackfph"))
1459 Diag(
Loc, diag::err_riscv_type_requires_extension,
D)
1460 << Ty <<
"zvfh, zvfhmin or xandesvpackfph";
1462 Diag(
Loc, diag::err_riscv_type_requires_extension,
D)
1463 << Ty <<
"zvfh or zvfhmin";
1466 !FeatureMap.lookup(
"zvfbfmin") &&
1467 !FeatureMap.lookup(
"xandesvbfhcvt"))
1469 Diag(
Loc, diag::err_riscv_type_requires_extension,
D)
1470 << Ty <<
"zvfbfmin or xandesvbfhcvt";
1472 Diag(
Loc, diag::err_riscv_type_requires_extension,
D) << Ty <<
"zvfbfmin";
1475 !FeatureMap.lookup(
"zve32f"))
1476 Diag(
Loc, diag::err_riscv_type_requires_extension,
D) << Ty <<
"zve32f";
1479 else if (!FeatureMap.lookup(
"zve32x"))
1480 Diag(
Loc, diag::err_riscv_type_requires_extension,
D) << Ty <<
"zve32x";
1492 auto ValidScalableConversion = [](
QualType FirstType,
QualType SecondType) {
1496 const auto *VecTy = SecondType->getAs<
VectorType>();
1500 return ValidScalableConversion(srcTy, destTy) ||
1501 ValidScalableConversion(destTy, srcTy);
1506 if (
const auto *A =
D->
getAttr<RISCVInterruptAttr>()) {
1508 diag::warn_riscv_repeated_interrupt_attribute);
1509 Diag(A->getLocation(), diag::note_riscv_repeated_interrupt_attribute);
1543 bool HasSiFiveCLICType =
false;
1544 bool HasUnaryType =
false;
1546 SmallSet<RISCVInterruptAttr::InterruptType, 2> Types;
1547 for (
unsigned ArgIndex = 0; ArgIndex < AL.
getNumArgs(); ++ArgIndex) {
1548 RISCVInterruptAttr::InterruptType
Type;
1549 StringRef TypeString;
1555 if (!RISCVInterruptAttr::ConvertStrToInterruptType(TypeString,
Type)) {
1556 std::string TypeLiteral = (
"\"" + TypeString +
"\"").str();
1557 Diag(AL.
getLoc(), diag::warn_attribute_type_not_supported)
1558 << AL << TypeLiteral <<
Loc;
1563 case RISCVInterruptAttr::machine:
1567 case RISCVInterruptAttr::SiFiveCLICPreemptible:
1568 case RISCVInterruptAttr::SiFiveCLICStackSwap:
1570 HasSiFiveCLICType =
true;
1572 case RISCVInterruptAttr::supervisor:
1573 case RISCVInterruptAttr::rnmi:
1574 case RISCVInterruptAttr::qcinest:
1575 case RISCVInterruptAttr::qcinonest:
1578 HasUnaryType =
true;
1585 if (HasUnaryType && Types.size() > 1) {
1586 Diag(AL.
getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);
1590 if (HasUnaryType && HasSiFiveCLICType) {
1591 Diag(AL.
getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);
1597 Types.insert(RISCVInterruptAttr::machine);
1600 llvm::StringMap<bool> FunctionFeatureMap;
1602 dyn_cast<FunctionDecl>(
D));
1604 auto HasFeature = [&](StringRef FeatureName) ->
bool {
1605 return TI.
hasFeature(FeatureName) || FunctionFeatureMap.lookup(FeatureName);
1608 for (RISCVInterruptAttr::InterruptType
Type : Types) {
1611 case RISCVInterruptAttr::qcinest:
1612 case RISCVInterruptAttr::qcinonest: {
1615 diag::err_riscv_attribute_interrupt_requires_extension)
1616 << RISCVInterruptAttr::ConvertInterruptTypeToStr(
Type) <<
"Xqciint";
1621 case RISCVInterruptAttr::SiFiveCLICPreemptible:
1622 case RISCVInterruptAttr::SiFiveCLICStackSwap: {
1625 diag::err_riscv_attribute_interrupt_requires_extension)
1626 << RISCVInterruptAttr::ConvertInterruptTypeToStr(
Type)
1631 case RISCVInterruptAttr::rnmi: {
1634 diag::err_riscv_attribute_interrupt_requires_extension)
1635 << RISCVInterruptAttr::ConvertInterruptTypeToStr(
Type) <<
"Smrnmi";
1660 if (!Ext.consume_front(
"+"))
1663 return -1 != RISCVISAInfo::getRISCVFeaturesBitsInfo(Ext).second;
1668 using namespace DiagAttrParams;
1671 Param.split(AttrStrs,
';');
1673 bool HasArch =
false;
1674 bool HasPriority =
false;
1675 bool HasDefault =
false;
1676 bool DuplicateAttr =
false;
1677 for (StringRef AttrStr : AttrStrs) {
1678 AttrStr = AttrStr.trim();
1680 if (AttrStr.starts_with(
"arch=+")) {
1681 DuplicateAttr = HasArch;
1687 llvm::any_of(TargetAttr.
Features, [&](
const StringRef Ext) {
1688 return !isValidFMVExtension(Ext);
1690 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1692 }
else if (AttrStr ==
"default") {
1693 DuplicateAttr = HasDefault;
1695 }
else if (AttrStr.consume_front(
"priority=")) {
1696 DuplicateAttr = HasPriority;
1699 if (AttrStr.getAsInteger(0, Digit))
1700 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1703 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1708 if (((HasPriority || HasArch) && HasDefault) || DuplicateAttr ||
1709 (HasPriority && !HasArch))
1710 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1719 using namespace DiagAttrParams;
1721 assert(Params.size() == Locs.size() &&
1722 "Mismatch between number of string parameters and locations");
1724 bool HasDefault =
false;
1725 for (
unsigned I = 0,
E = Params.size(); I <
E; ++I) {
1726 const StringRef Param = Params[I].trim();
1730 Param.split(AttrStrs,
';');
1732 bool IsPriority =
false;
1733 bool IsDefault =
false;
1734 for (StringRef AttrStr : AttrStrs) {
1735 AttrStr = AttrStr.trim();
1737 if (AttrStr.starts_with(
"arch=+")) {
1742 llvm::any_of(TargetAttr.
Features, [&](
const StringRef Ext) {
1743 return !isValidFMVExtension(Ext);
1745 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1747 }
else if (AttrStr ==
"default") {
1750 }
else if (AttrStr.consume_front(
"priority=")) {
1753 if (AttrStr.getAsInteger(0, Digit))
1754 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1757 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1762 if (IsPriority && IsDefault)
1763 return Diag(
Loc, diag::warn_unsupported_target_attribute)
1766 if (llvm::is_contained(NewParams, Param))
1767 Diag(
Loc, diag::warn_target_clone_duplicate_options);
1768 NewParams.push_back(Param);
1771 return Diag(Locs[0], diag::err_target_clone_must_have_default);
Defines the clang::ASTContext interface.
Defines enum values for all the target-independent builtin functions.
llvm::MachO::Record Record
static bool HasFeature(const Preprocessor &PP, StringRef Feature)
HasFeature - Return true if we recognize and implement the feature specified by the identifier as a s...
Defines the clang::Preprocessor interface.
static const RVVIntrinsicRecord RVSiFiveVectorIntrinsicRecords[]
static const RVVIntrinsicRecord RVAndesVectorIntrinsicRecords[]
static const PrototypeDescriptor RVAndesVectorSignatureTable[]
static const RVVIntrinsicRecord RVVIntrinsicRecords[]
static const PrototypeDescriptor RVSiFiveVectorSignatureTable[]
static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type)
static ArrayRef< PrototypeDescriptor > ProtoSeq2ArrayRef(IntrinsicKind K, uint16_t Index, uint8_t Length)
static const PrototypeDescriptor RVVSignatureTable[]
This file declares semantic analysis functions specific to RISC-V.
Enumerates target-specific builtins in their own namespaces within namespace clang.
Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...
BuiltinVectorTypeInfo getBuiltinVectorTypeInfo(const BuiltinType *VecTy) const
Returns the element type, element count and number of vectors (in case of tuple) for a builtin vector...
TranslationUnitDecl * getTranslationUnitDecl() const
QualType getScalableVectorType(QualType EltTy, unsigned NumElts, unsigned NumFields=1) const
Return the unique reference to a scalable vector type of the specified element type and scalable numb...
QualType getPointerType(QualType T) const
Return the uniqued reference to the type for a pointer to the specified type.
QualType getConstType(QualType T) const
Return the uniqued reference to the type for a const qualified type.
QualType getPointerDiffType() const
Return the unique type for "ptrdiff_t" (C99 7.17) defined in <stddef.h>.
QualType getIntTypeForBitwidth(unsigned DestWidth, unsigned Signed) const
getIntTypeForBitwidth - sets integer QualTy according to specified details: bitwidth,...
CanQualType UnsignedLongTy
uint64_t getTypeSize(QualType T) const
Return the size of the specified (complete) type T, in bits.
QualType getFunctionType(QualType ResultTy, ArrayRef< QualType > Args, const FunctionProtoType::ExtProtoInfo &EPI) const
Return a normal function type with a typed argument list.
QualType getSizeType() const
Return the unique type for "size_t" (C99 7.17), defined in <stddef.h>.
const TargetInfo & getTargetInfo() const
void getFunctionFeatureMap(llvm::StringMap< bool > &FeatureMap, const FunctionDecl *) const
SourceRange getRange() const
bool isRegularKeywordAttribute() const
SourceLocation getLoc() const
This class is used for builtin types like 'int'.
CallExpr - Represents a function call (C99 6.5.2.2, C++ [expr.call]).
Expr * getArg(unsigned Arg)
getArg - Return the specified argument.
SourceLocation getBeginLoc() const
void setArg(unsigned Arg, Expr *ArgExpr)
setArg - Set the specified argument.
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this call.
DeclContext - This is used only as base class of specific decl types that can act as declaration cont...
A reference to a declared variable, function, enum, etc.
SourceLocation getBeginLoc() const
Decl - This represents one declaration (or definition), e.g.
const FunctionType * getFunctionType(bool BlocksToo=true) const
Looks through the Decl's underlying type to extract a FunctionType when possible.
SourceLocation getLocation() const
This represents one expression.
Expr * IgnoreParenCasts() LLVM_READONLY
Skip past any parentheses and casts which might surround this expression until reaching a fixed point...
bool isValueDependent() const
Determines whether the value of this expression depends on.
bool isTypeDependent() const
Determines whether the type of this expression depends on.
bool isFPConstrained() const
Represents a function declaration or definition.
static FunctionDecl * Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation NLoc, DeclarationName N, QualType T, TypeSourceInfo *TInfo, StorageClass SC, bool UsesFPIntrin=false, bool isInlineSpecified=false, bool hasWrittenPrototype=true, ConstexprSpecKind ConstexprKind=ConstexprSpecKind::Unspecified, const AssociatedConstraint &TrailingRequiresClause={})
One of these records is kept for each identifier that is lexed.
StringRef getName() const
Return the actual identifier string.
IdentifierInfo & get(StringRef Name)
Return the identifier token info for the specified named identifier.
Describes an entity that is being initialized.
static InitializedEntity InitializeParameter(ASTContext &Context, ParmVarDecl *Parm)
Create the initialization entity for a parameter.
Represents the results of name lookup.
void addDecl(NamedDecl *D)
Add a declaration to these results with its natural access.
void resolveKind()
Resolves the result kind of the lookup, possibly hiding decls.
SourceLocation getNameLoc() const
Gets the location of the identifier.
Represents a parameter to a function.
void setScopeInfo(unsigned scopeDepth, unsigned parameterIndex)
static ParmVarDecl * Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, StorageClass S, Expr *DefArg)
ParsedAttr - Represents a syntactic attribute.
unsigned getNumArgs() const
getNumArgs - Return the number of actual arguments to this attribute.
bool checkAtMostNumArgs(class Sema &S, unsigned Num) const
Check if the attribute has at most as many args as Num.
PointerType - C99 6.7.5.1 - Pointer Declarators.
QualType getPointeeType() const
Engages in a tight little dance with the lexer to efficiently preprocess tokens.
IdentifierTable & getIdentifierTable()
A (possibly-)qualified type.
const Type * getTypePtr() const
Retrieves a pointer to the underlying (unqualified) type.
QualType getCanonicalType() const
QualType getUnqualifiedType() const
Retrieve the unqualified variant of the given type, removing as little sugar as possible.
static llvm::SmallVector< Policy > getSupportedMaskedPolicies(bool HasTailPolicy, bool HasMaskPolicy)
static llvm::SmallVector< PrototypeDescriptor > computeBuiltinTypes(llvm::ArrayRef< PrototypeDescriptor > Prototype, bool IsMasked, bool HasMaskedOffOperand, bool HasVL, unsigned NF, PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple)
static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, std::string &OverloadedName, Policy &PolicyAttrs, bool HasFRMRoundModeOp)
static std::string getSuffixStr(RVVTypeCache &TypeCache, BasicType Type, int Log2LMUL, llvm::ArrayRef< PrototypeDescriptor > PrototypeDescriptors)
static llvm::SmallVector< Policy > getSupportedUnMaskedPolicies()
SemaDiagnosticBuilder Diag(SourceLocation Loc, unsigned DiagID, bool DeferHint=false)
Emit a diagnostic.
ASTContext & getASTContext() const
bool CheckBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall)
bool CheckLMUL(CallExpr *TheCall, unsigned ArgNum)
bool isAliasValid(unsigned BuiltinID, llvm::StringRef AliasName)
bool isValidFMVExtension(StringRef Ext)
bool DeclareAndesVectorBuiltins
Indicate RISC-V Andes vector builtin functions enabled or not.
bool DeclareSiFiveVectorBuiltins
Indicate RISC-V SiFive vector builtin functions enabled or not.
void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D, const llvm::StringMap< bool > &FeatureMap)
bool isValidRVVBitcast(QualType srcType, QualType destType)
Are the two types RVV-bitcast-compatible types? I.e.
void handleInterruptAttr(Decl *D, const ParsedAttr &AL)
bool checkTargetClonesAttr(SmallVectorImpl< StringRef > &Params, SmallVectorImpl< SourceLocation > &Locs, SmallVectorImpl< SmallString< 64 > > &NewParams)
bool DeclareRVVBuiltins
Indicate RISC-V vector builtin functions enabled or not.
bool checkTargetVersionAttr(const StringRef Param, const SourceLocation Loc)
Sema - This implements semantic analysis and AST building for C.
bool checkArgCountAtMost(CallExpr *Call, unsigned MaxArgCount)
Checks that a call expression's argument count is at most the desired number.
FunctionDecl * getCurFunctionDecl(bool AllowLambda=false) const
Returns a pointer to the innermost enclosing function, or nullptr if the current context is not insid...
ExprResult DefaultFunctionArrayLvalueConversion(Expr *E, bool Diagnose=true)
FPOptions & getCurFPFeatures()
bool checkArgCountAtLeast(CallExpr *Call, unsigned MinArgCount)
Checks that a call expression's argument count is at least the desired number.
bool BuiltinConstantArg(CallExpr *TheCall, int ArgNum, llvm::APSInt &Result)
BuiltinConstantArg - Handle a check if argument ArgNum of CallExpr TheCall is a constant expression.
ExprResult PerformCopyInitialization(const InitializedEntity &Entity, SourceLocation EqualLoc, ExprResult Init, bool TopLevelOfInitList=false, bool AllowExplicit=false)
bool BuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, int Low, int High, bool RangeIsError=true)
BuiltinConstantArgRange - Handle a check if argument ArgNum of CallExpr TheCall is a constant express...
bool checkStringLiteralArgumentAttr(const AttributeCommonInfo &CI, const Expr *E, StringRef &Str, SourceLocation *ArgLocation=nullptr)
Check if the argument E is a ASCII string literal.
Encodes a location in the source.
SourceLocation getBegin() const
SourceRange getSourceRange() const LLVM_READONLY
SourceLocation tokens are not useful in isolation - they are low level value objects created/interpre...
Exposes information about the current target.
virtual CallingConv getDefaultCallingConv() const
Gets the default calling convention for the given target.
virtual ParsedTargetAttr parseTargetAttr(StringRef Str) const
virtual bool hasFeature(StringRef Feature) const
Determine whether the given target has the given feature.
The base class of the type hierarchy.
bool isBlockPointerType() const
bool isFloat16Type() const
bool isIntegerType() const
isIntegerType() does not include complex integers (a GCC extension).
const T * castAs() const
Member-template castAs<specific type>.
bool isSpecificBuiltinType(unsigned K) const
Test for a particular builtin type.
bool isBFloat16Type() const
bool isVectorType() const
bool isRVVSizelessBuiltinType() const
Returns true for RVV scalable vector types.
bool isFloatingType() const
bool isAnyPointerType() const
const T * getAs() const
Member-template getAs<specific type>'.
Represents a GCC generic vector type.
VectorKind getVectorKind() const
virtual bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II, Preprocessor &PP)=0
virtual void InitIntrinsicList()=0
Defines the clang::TargetInfo interface.
std::vector< RVVTypePtr > RVVTypes
The JSON file list parser is used to communicate input to InstallAPI.
QualType getFunctionOrMethodResultType(const Decl *D)
std::unique_ptr< sema::RISCVIntrinsicManager > CreateRISCVIntrinsicManager(Sema &S)
@ Result
The result type of a method or function.
static bool CheckInvalidVLENandLMUL(const TargetInfo &TI, llvm::StringMap< bool > &FunctionFeatureMap, CallExpr *TheCall, Sema &S, QualType Type, int EGW)
bool hasFunctionProto(const Decl *D)
hasFunctionProto - Return true if the given decl has a argument information.
unsigned getFunctionOrMethodNumParams(const Decl *D)
getFunctionOrMethodNumParams - Return number of function or method parameters.
@ RVVFixedLengthData
is RISC-V RVV fixed-length data vector
@ None
The alignment was not explicit in code.
Diagnostic wrappers for TextAPI types for error reporting.
Extra information about a function prototype.
Contains information gathered from parsing the contents of TargetAttr.
std::vector< std::string > Features