Wikipedia

z/Architecture

This article is about z/Architecture mode. For z/Architecture in ESA/390 mode, see ESA/390.

z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000.[1] Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15 and z16.

z/Architecture
DesignerIBM
Bits64-bit
Introduced2000; 24 years ago (2000)
VersionARCHLVL 2 and ARCHLVL 3 (2008)
DesignCISC
TypeRegister–Register
Register–Memory
Memory–Memory
EncodingVariable (2, 4 or 6 bytes long)
BranchingCondition code, indexing, counting
EndiannessBig
PredecessorESA/390
Registers
Access 16× 32, breaking-event-address register (BEAR) 64-bit, Control 16×64, Floating Point Control 32-bit, Prefix 64 bit, PSW 128-bit
General-purpose16× 64-bit
Floating point16× 64-bit
Vector32× 128-bit, VR0-VR15 contain FPR0-FPR15

z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors back to the 32-bit-data/24-bit-addressing System/360. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode.[2] However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.

Features

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z/Architecture includes almost all[a] of the features of ESA/390, and adds some new features. Among the features[b] of z/Architecture are

A channel subsystem with the architecture introduced by S/370-XA
Branch relative instructions introduced by ESA/390
Trimodal (24/31/64-bit) addresses
16 32-bit access registers (ARs) introduced by ESA/370
16 64-bit general registers (GRs)
16 64-bit control registers (CRs) introduced by System/370
16 64-bit floating-point registers (FPRs)
32 128-bit vector registers (VRs); bits 0-63 of VR0-VR15 contain FPR0-FPR15
1 32-bit floating point control (FPC) register
1 128-bit processor status register (PSW), which includes a 64-bit instruction address
An 8-KiB prefix storage area (PSA)
Cryptographic Facility
IEEE Binary-floating-point instructions added by ESA/390
IEEE Decimal-floating point instructions

For information on when each feature was introduced, consult Principles of operation.[3][4]

Registers

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IBM z/Architecture registers
General Registers 0-15

Two's complement value
0 31

Two's complement value (continued)
32 63
Access Registers 0-15[5]

0 0 0 0 0 0 0 P ALESN ALEN
0 6 7 8 15 16 31
z/Architecture Access register abbreviations
Bits Field Meaning
0-6 0000000
7 P Primary
0=use dispatchable-unit access list
1=use primary-space access list
8-15 ALESN access-list-entry sequence number
16-31 ALEN access-list-entry number
Breaking-event-address register (BEAR)

See Principles of Operation[6]
0 31
(continued)
32 63
Control Registers 0-15

See Principles of Operation[7] or Control Registers
0 31
(continued)
32 63
Floating Point Registers (hexadecimal) 0-15

S Biased exponent Mantissa
0 1 7 8 31

Mantissa (continued)
32 63
Floating Point Registers (binary, single precision) 0-15

S Biased exponent Mantissa
0 1 8 9 31
Floating Point Registers (binary, double precision) 0-15

S Biased exponent Mantissa
0 1 11 12 31

Mantissa (continued)
32 63
Prefix register[8]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 31
0 Prefix Bits 33-50 0 n/a
32 33 50 51 52 63
z/Architecture long PSW[9]

0 R 0 0 0 T I
O 		E
X 		Key 0 M W P AS CC Program
Mask 		R
I 		0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 30 31

B
A 		0
32 33 63

Instruction Address
64 95

Instruction Address (Continued)
96 127
Long PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=0 Must be zero for LPSWE
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
64-127 IA Instruction Address
z/Architecture short PSW[10]

0 R 0 0 0 T I
O 		E
X 		Key 1 M W P AS CC Program
Mask 		R
I 		0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 25 30 31

B
A 		Instruction Address
32 33 63
Short PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=1 Must be one for LPSW
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
33-63 IA Instruction Address

Each processor has these registers

Access registers

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Each CPU has 16 32-bit access registers.[5][11] When a program running in AR mode specifies register 1-15 as a base register or as a register operand containing an address, the CPU uses the associated access register during address translation.

Breaking-event-address register (BEAR)

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The 64-bit BEAR[6][12] contains the address of the last instruction that broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 (11016). After an Execute of a branch, the BEAR contains the address of the execute, not that of the branch.

Control registers

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The 16 64-bit control registers provide controls over and the status of a CPU, except for information included in the PSW. They are an evolutionary enhancement to the control registers on the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.[13] Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

z/Architecture mode control registers
CR bits Field
0 8 Transactional-execution control
0 9 Transactional-execution program-interruption filtering override
0 10 Clock-comparator sign control
0 13 Cryptography counter controll
0 14 Processor-activity-instrumentation-extension control
0 15 Measurement-counter-extraction-authorization control
0 30 Warning-track subclass mask
0 32 TRACE TOD-clock control
0 33 SSM-suppression
0 34 TOD-clock-sync control
0 35 Low-address-protection control
0 36 Extraction-authority control
0 37 Secondary-space control
0 38 Fetch-protection-override control
0 39 Storage-protection-override control
0 40 Enhanced-DAT-enablement control
0 43 Instruction-execution-protection-enablement control
0 44 ASN-and-LX-reuse control
0 45 AFP-register control
0 46 Vector enablement control
0 48 Malfunction-alert subclass mask
0 48 Malfunction-alert subclass mask
0 49 Emergency-signal subclass mask
0 50 External-call subclass mask
0 52 Clock-comparator subclass mask
0 53 CPU-timer subclass mask
0 54 Service-signal subclass mask
0 56 Initialized to 1
0 57 Interrupt-key subclass mask
0 58 Measurement-alert subclass mask
0 59 Timing-alert subclass mask
0 61 Crypto control
1 0-51 Primary Address-Space Control Element (ASCE)
Primary region-table origin
Primary segment-table origin
Primary real-space token origin
1 54 Primary subspace-group control
1 55 Primary private-space control
1 56 Primary storage-alteration-event
1 57 Primary space-switch-event control
1 58 Primary real-space control
1 60-61 Primary designation-type control
1 62-63 Primary table length
2 33-57 Dispatchable-unit-control-table origin
2 59 Guarded-storage-facility enablement control
2 61 Transaction diagnostic scope
2 62-63 Transaction diagnostic control
3 0-31 Secondary ASN-second-table-entry instance number
3 32-47 PSW-key mask
3 48-63 Secondary ASN
4 0-31 Primary ASN-second-table-entry instance number
4 32-47 Authorization index
4 48-63 Primary ASN
5 33-57 Primary-ASN-second-table-entry origin
6 32-39 I/O-interruption subclass mask
7 0-51 Secondary Address-Space Control Element (ASCE)
Secondary region-table origin
Secondary segment-table origin
Secondary real-space token origin
7 54 Secondary subspace-group control
7 55 Secondary private-space control
7 56 Secondary storage-alteration-event control
7 58 Secondary real-space control
7 60-61 Secondary designation-type control
7 62-63 Secondary table length
8 16-31 Enhanced-monitor masks
8 32-47 Extended authorization index
8 48-63 Monitor masks
9 32 Successful-branching-event mask
9 33 Instruction-fetching-event mask
9 34 Storage-alteration-event mask
9 35 Storage-key-alteration-event mask
9 36 Store-using-real-address-event mask
9 37 Zero-address-detection-event mask
9 38 Transaction-end event mask
9 39 Instruction-fetching-nullification-event mask
9 40 Branch-address control
9 41 PER-event-suppression control
9 43 Storage-alteration-space control
10 0-63 PER starting address
11 0-63 PER ending address
12 0 Branch-trace control
12 1 Mode-trace control
12 2-61 Trace-entry address
12 62 ASN-trace control
12 63 Explicit-trace control
13 0-51 Home Address-Space Control Element (ASCE)
Home region-table origin
Home segment-table origin
Home real-space token origin
13 55 Home private-space control
13 56 Home storage-alteration-eventl
13 57 Home space-switch-event control
13 58 Secondary real-space control
13 60-61 Home designation-type control
13 62-63 Home table length
14 32 Set to 1
14 33 Set to 1
14 34 Extended save-area control (ESA/390-compatibility mode

only)

14 35 Channel-report-pending subclass mask
14 36 Recovery subclass mask
14 37 Degradation subclass mask
14 38 External-damage subclass mask
14 39 Warning subclass mask
14 42 TOD-clock-control-override control
14 44 ASN-translation control
14 45-63 ASN-first-table origin
15 0-60 Linkage-stack-entry address

Floating point Control (FPC) register

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The FPC register contains Interrupt Masks (IM), Status Flags (SF), Data Exception Code (DXC), Decimal Rounding Mode (DRM) and Binary Rounding Mode (BRM). An interruption only stores the DXC if the FPC register if the AFP-register (additional floating-point register) control bit, bit 13 of control register 0, is one. Also, while individual bits of the DXC usually have significance, programs should normally treat it as an 8-bit integer rather than querying individual bits.

FPC fields
Byte name Bits Field name Use
masks 0 IMi IEEE-invalid-operation mask
masks 1 IMz IEEE-division-by-zero mask
masks 2 IMo IEEE-overflow mask
masks 3 IMu IEEE-underflow mask
masks 4 IMx IEEE-inexact mask
masks 5 IMq Quantum-exception mask
flags 8 SFi IEEE-invalid-operation flag
flags 9 SFz IEEE-division-by-zero
flags 10 SFo IEEE-overflow flag
flags 11 SFu IEEE-underflow flag
flags 12 SFx IEEE-inexact flag
flags 13 SFq Quantum-exception flag
DXC 16-23 DXC Data-exception code
DXC 16 i IEEE-invalid-operation
DXC 17 z IEEE-division-by-zero
DXC 18 o IEEE-overflow
DXC 19 u IEEE-underflow mask
DXC 20 x IEEE-inexact mask
DXC 21 y/q Quantum-exception mask
25-27 DRM DFP rounding mode
29-31 BRM BFP rounding mode

Floating point registers

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Each CPU had 16 64-bit floating point registers; FP0-15 occupy bits 0-63 of VR0-15.

General registers

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Each CPU has 16 64-bit general registers, which serve as accumulators, base registers[c] and index registers.[c] Instructions designated as Grandé operate on all 64 bits; some instructions added by the Extended-Immediate Facility operate on any halfword or word in the register; most other instructions do not change or use bits 0-31.

Prefix register

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The prefix register is used in translating a real address to an absolute address. In z/Architecture mode, the PSA is 2 pages (8 KiB). Bits 0-32 and 51-63 are always zero. If bits 0-50 of a real address are zero then they are replaced by bits 0-50 of the prefix register; if bits 0-50 of the real address are equal to bits 0-50 of the prefix register then they are replaced with zeros.

Program status word (PSW)

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The PSW holds the instruction address and other fields reflecting the status of the program currently running on a CPU. The status of the program is also affected by the contents of the Control registers.

Vector registers

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Each CPU has 32 128-bit vector registers.{{sfn|z|loc=Vector Registers|pp=2-5–2-6 bits 0-63 of VR0-15 are also FPR0-15. A vector register may contain 16 8-bit fields, 8 16-bit fields, 4 32-bit fields, 2 64-bit fields or 1 128-bit field.

Memory

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IBM classifies memory in z/Architecture into Main Storage and Expanded Storage.

Main storage is addressed in 8-bit bytes (octets), with larger aligned[d] groupings:

Halfword
Two bytes
16 bits
Word
Four bytes
32 bits
Doubleword
8 bytes
64 bits
Quadword
16 bytes
128 bits
Page
4096 bytes

Although z/Architecture allows real and virtual addresses from 0 to 264-1, engineering constraints limit current and planned models to far less.

Expanded storage is address in 4 KiB blocks, with block numbers ranging fom 0 to 232.

Addressing

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Types of main storage addresses

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There are three types of main storage addresses in z/Architecture

Virtual address
The address as seen by application programs. It is an offset into an address space and is subject to address translation via page and segment tables.
Real address
The address after address translation, or the address seen by an OS component running with translation off. It is subject to prefixing.
Absolute address
The address after prefixing references to the first two pages[e] via the prefix register.

Address encoding

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z/Architecture uses the same truncated addressing as ESA, with some additional instruction formats. As with ESA, in AR mode each nonzero base register is associated with a base register specifying the address space. Depending on the instruction, an address may be provided in several different formats.

R
The address is contained in a general register
Relative
A signed 16-bit halfword offset from the current instruction.
Relative long
A signed 32-bit halfword offset from the current instruction.
RS
A base register and a 12-bit displacement
RX
A base register, an index register, and a 12-bit displacement
Y
A base register, an index register, and a 20-bit displacement; colloquially known as "Yonder".

Addressing modes

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In addition to the two addressing modes supported by S/370-XA and ESA, a/Architecture has an extended addressing mode with 64-bit virtual addresses. The addressing mode is controlled by the EA (bit 31) and BA (bit 32) bits in the PSW. The valid combinations are

  • 00 24-bit addressing
  • 01 31-bit addressing
  • 11 64-bit addressing

Translation modes

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z/Architecture supports four virtual translation modes, controlled by[14] bit 5, the DAT-mode bit, and bits 16-17, the Address-Space Control (AS) bits, of the PSW.

Primary-space mode
All storage references use the translation tables for the primary address space
Access-register mode
All storage references use the translation tables designated by the access register associated with the base register.
Secondary-space mode
All storage references use the translation tables for the secondary address space
Home-space mode
All storage references use the translation tables for the home address space

Operating system support

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IBM's operating systems z/OS, z/VSE, z/TPF, and z/VM are versions of MVS, VSE, Transaction Processing Facility (TPF), and VM that support z/Architecture. Older versions of z/OS, z/VSE, and z/VM continued to support 32-bit systems; z/OS version 1.6 and later, z/VSE Version 4 and later, and z/VM Version 5 and later require z/Architecture.

Linux also supports z/Architecture with Linux on IBM Z.

z/Architecture supports running multiple concurrent operating systems and applications even if they use different address sizes. This allows software developers to choose the address size that is most advantageous for their applications and data structures.

On July 7, 2009, IBM on occasion of announcing a new version of one of its operating systems implicitly stated that Architecture Level Set 4 (ALS 4) exists, and is implemented on the System z10 and subsequent machines.[15][16] The ALS 4 is also specified in LOADxx as ARCHLVL 3, whereas the earlier z900, z800, z990, z890, System z9 specified ARCHLVL 2. Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating point unit (HDFU).[17][18]

Most[citation needed] operating systems for the z/Architecture, including z/OS, generally restrict code execution to the first 2 GB (31 address bits, or 231 addressable bytes) of each virtual address space for reasons of efficiency and compatibility rather than because of architectural limits. Linux on IBM Z allows code to execute within 64-bit address ranges.

z/OS

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Each z/OS address space, called a 64-bit address space, is 16 exabytes in size.

Code (or mixed) spaces

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The z/OS implementation of the Java programming language is an exception. The z/OS virtual memory implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code.

Data-only spaces

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Data-only spaces are memory regions that can be read from and written to, but not used as executable code. (Similar to the NX bit on other modern processors.) By default, the z/Architecture memory space is indexed by 64-bit pointers, allowing up to 16 exabytes of memory to be visible to an executing program.

Dataspaces and hiperspaces
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Applications that need more than a 16 exabyte data address space can employ extended addressability techniques, using additional address spaces or data-only spaces. The data-only spaces that are available for user programs are called:

  • dataspaces (sometimes referred to as "data spaces")[19][20] and
  • hiperspaces (High performance space).[21][22]

These spaces are similar in that both are areas of virtual storage that a program can create, and can be up to 2 gigabytes. Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas. Program code cannot run in a dataspace or a hiperspace.[23]

A dataspace differs from a hiperspace in that dataspaces are byte-addressable, whereas hiperspaces are page-addressable.

IBM mainframe expanded storage

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Traditionally IBM Mainframe memory has been byte-addressable. This kind of memory is termed "Central Storage". IBM Mainframe processors through much of the 1980s and 1990s supported another kind of memory: Expanded Storage. It was first introduced with the IBM 3090 high-end mainframe series in 1985.[24]

Expanded Storage is 4KB-page addressable. When an application wants to access data in Expanded Storage it must first be moved into Central Storage. Similarly, data movement from Central Storage to Expanded Storage is done in multiples of 4KB pages. Initially page movement was performed using relatively expensive instructions, by paging subsystem code.

The overhead of moving single and groups of pages between Central and Expanded Storage was reduced with the introduction of the MVPG (Move Page) instruction and the ADMF (Asynchronous Data Mover Facility) capability.

The MVPG instruction and ADMF are explicitly invoked—generally by middleware in z/OS or z/VM (and ACP?)—to access data in expanded storage. Some uses are namely:

  • MVPG is used by VSAM Local Shared Resources (LSR) buffer pool management to access buffers in a hiperspace in Expanded Storage.
  • Both MVPG and ADMF are used by IBM Db2 to access hiperpools. Hiperpools are portions of a buffer pool located in a hiperspace.
  • VM Minidisk Caching.

Until the mid-1990s Central and Expanded Storage were physically different areas of memory on the processor. Since the mid-1990s Central and Expanded Storage were merely assignment choices for the underlying processor memory. These choices were made based on specific expected uses: For example, Expanded Storage is required for the Hiperbatch function (which uses the MVPG instruction to access its hiperspaces).

In addition to the hiperspace and paging cases mentioned above there are other uses of expanded storage, including:

  • Virtual I/O (VIO) to Expanded Storage which stored temporary data sets in simulated devices in Expanded Storage. (This function has been replaced by VIO in Central Storage.)
  • VM Minidisk Caching.

z/OS removed the support for Expanded Storage. All memory in z/OS is now Central Storage. z/VM 6.4 fulfills Statement of Direction to drop support for all use of Expanded Storage.

MVPG and ADMF

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MVPG

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IBM described MVPG as "moves a single page and the central processor cannot execute any other instructions until the page move is completed."[25]

The MVPG mainframe instruction[26] (MoVe PaGe, opcode X'B254') has been compared to the MVCL (MoVe Character Long) instruction, both of which can move more than 256 bytes within main memory using a single instruction. These instructions do not comply with definitions for atomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.[27]: Note 8, page 7–27 [28]

The need to move more than 256 bytes within main memory had historically been addressed with software[29] (MVC loops), MVCL,[30] which was introduced with the 1970 announcement of the System/370, and MVPG, patented[31] and announced by IBM in 1989, each have advantages.[32]

ADMF

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ADMF (Asynchronous Data Mover Facility), which was introduced in 1992, goes beyond the capabilities of the MVPG (Move Page) instruction, which is limited to a single page,[33] and can move groups of pages between Central and Expanded Storage.

A macro instruction named IOSADMF, which has been described as an API that avoids "direct, low-level use of ADMF",[34] can be used to read[f] or write data to or from a hiperspace.[35] Hiperspaces are created using DSPSERV CREATE.

To provide reentrancy, IOSADMF is used together with a "List form" and "Execute form."[36]

Non-IBM implementations

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Platform Solutions Inc. (PSI) previously marketed Itanium-based servers which were compatible with z/Architecture. IBM bought PSI in July 2008, and the PSI systems are no longer available.[37] FLEX-ES, zPDT and the Hercules emulator also implement z/Architecture. Hitachi mainframes running newer releases of the VOS3 operating system implement ESA/390 plus Hitachi-unique CPU instructions, including a few 64-bit instructions. While Hitachi formally collaborated with IBM on the z900-G2/z800 CPUs introduced in 2002, Hitachi's machines are not z/Architecture-compatible.

Notes

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  1. ^ The ESA asynchronous-pageout, asynchronous-data-mover, program-call-fast, and ESA/390 vector facilities are not present in z/Architecture. The z/Architecture vector feature has been replaced by a very different vector facility.
  2. ^ For a complete list see Chapter 1. Introduction in Principle of Operation.[3][4]
  3. ^ a b Except for general register 0.
  4. ^ Some instructions allow references to unaligned data.
  5. ^ References to the first page in ESA mode, but that is not available on current models.
  6. ^ AREAD - transfer data from a hiperspace to the program's primary address space.

References

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z
z/Architecture Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. SA22-7832-13. Retrieved June 28, 2024.
  1. ^ Development and Attributes of z/Architecture Archived 2013-12-12 at the Wayback Machine, IBM Journal of Research and Development, 2002.
  2. ^ "Accommodate functions for the z13 server to be discontinued on future servers". IBM. 25 June 2015. Archived from the original on 2017-09-15. Retrieved 2017-09-18.
  3. ^ a b z, pp. 1-2–1-7, Highlights of Original z/Architecture.
  4. ^ a b z, pp. 1-7–1-31, Additions to z/Architecture.
  5. ^ a b z, p. 5-50, Access-Register-Specified Address Spaces.
  6. ^ a b z, p. 4-46, Breaking-Event-Address Register.
  7. ^ z, pp. 4-9–4-11, Figure 4-5. Assignment of Control-Register Fields.
  8. ^ z, pp. 3-22–3-23, Prefixing in the z/Architecture Architectural Mode.
  9. ^ z, pp. 4-5–4-8, Program-Status-Word Format.
  10. ^ z, p. 4-8, Short PSW Format.
  11. ^ z, pp. 6-15–6-16, Access Registers.
  12. ^ z, p. 4-464-46, Breaking-Event-Address Register.
  13. ^ z, pp. 4-9–4-12, Control Registers.
  14. ^ z, pp. 3-41, 3-42, Figure 3-15. Translation Modes.
  15. ^ Preview: IBM z/VM V6.1 - Foundation for future virtualization growth Archived 2021-10-28 at the Wayback Machine, IBM United States Software Announcement 209-207, dated July 7, 2009
  16. ^ ALS 1 was 9672 G2; ALS 2 was 9672 G5; ALS 3 was the original z/Architecture:"IBM CMOS Processor Table". 18 November 2008. Archived from the original on 10 December 2013. Retrieved 18 October 2012.
  17. ^ "IBM System z10 Business Class (z10 BC) Reference Guide" (PDF). IBM. 2008. Archived (PDF) from the original on 2011-03-04. Retrieved 2012-10-18.
  18. ^ "z/Architecture Principles of Operation" (PDF). Archived (PDF) from the original on 2020-11-30. Retrieved 2016-01-15.
  19. ^ Hoskins, Jim; Frank, Bob (2002). Exploring IBM Eserver Zseries and S/390 Servers. Maximum Press. p. 26. ISBN 1885068913. Archived from the original on 2021-04-27. Retrieved 2017-10-19. VM Data Spaces architecture is standard on all System/390 processors.
  20. ^ "CA Defends VSE Policy". InformationWeek. October 21, 1991. p. 15. Computer Associates International is now providing data space technology to VSE/ESA or System/370 users.
  21. ^ "Analyzing data in memory". IBM.
  22. ^ Hemanth Nandas (October 15, 2007). "What is hiperspace? Which was the first OS to support hiperspace?". Newsgroup: ibmmainframes.com. Archived from the original on February 2, 2017. Retrieved January 25, 2017. HIGH PERFORMANCE SPACE or "High Performance Dataspace" (author Anuj Dhawan, same date)
  23. ^ "CheatSheet #54 zTidBits z/OS Extended Addressing" (PDF). Retrieved 2022-07-17.
  24. ^ Sakaki, M.; Samukawa, H.; Honjou, N. (1988). "Effective utilization of IBM 3090 large virtual storage in the numerically intensive computations of ab initio molecular orbitals". IBM Systems Journal. 27 (4): 528–540. doi:10.1147/sj.274.0528. ISSN 0018-8670.
  25. ^ US 5442802  Asynchronous co-processor data mover method and means
  26. ^ "HLASM - MVPG = MoVe PaGe". Archived from the original on 2013-10-06. Retrieved 2017-01-24.
  27. ^ MOVE LONG, note 8."GA22-7000-10, IBM System/370, Principles of Operation" (PDF). Archived (PDF) from the original on 2021-04-11. Retrieved 2021-10-11.
  28. ^ "things are done immediately, and there is no chance of the instruction being half-completed or of another being interspersed. Used especially to convey that an operation cannot be interrupted.""Atomic from FOLDOC".
  29. ^ "$MVCL – Move more than 256 bytes of storage". IBM. 20 September 2014. Archived from the original on 2 February 2017. Retrieved 24 January 2017.
  30. ^ "Move Long". Archived from the original on 2017-04-27. Retrieved 2017-01-24.
  31. ^ US 5237668  Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
  32. ^ "MVPG faster than MVCL for aligned pages?". IBM-MAIN (Mailing list). Archived from the original on 2011-01-22. Retrieved 2017-01-24.
  33. ^ IBM's patent EP0549924A1 describes MVPG as "moves a single page."
  34. ^ Celestini, Art (Aug 20, 1997). "admf". IBM-MAIN (Mailing list). Archived from the original on 2011-01-22. Retrieved 2017-01-24 – via Google Groups.
  35. ^ z/OS MVS Programming: Extended Addressability Guide - SA23-1394-00
  36. ^ "IOSADMF — Transfer hiperspace data". IBM. 7 February 2015. Archived from the original on 2 February 2017. Retrieved 24 January 2017.
  37. ^ "IBM Acquires Platform Solutions" (Press release). IBM. 2008-07-02. Archived from the original on 2008-09-05. Retrieved 2008-09-06.

Further reading

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