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AnoushkaTripathi/README.md

Hi there, I'm Anoushka Tripathi! 👋

Screenshot 2025-02-27 100617 Welcome to my GitHub profile! I'm a passionate VLSI engineer with a love for designing and optimizing digital circuits and systems.

Presently working as FPGA Trainee at SSPL,DRDO

DIR-V SYMPOSIUM HACKATHON WINNER 2025 : Core/SoC Enhancement

WhatsApp Image 2025-03-08 at 7 57 38 AM (1)

🛠️ Technologies & Tools

FPGA VIVADO HLS Machine Learning Verilog RISC-V Python Git C C++

🚀 Projects

💬 Get in Touch

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  1. NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING Public

    In this VLSI design course, we explored topics such as HLS programming, combination circuits, sequential circuits, and a capstone project. From high-level synthesis to hands-on application, this co…

    C++ 7

  2. VSD_SQUADRON_MINI_RISCV_RESEARCH_INTERNSHIP VSD_SQUADRON_MINI_RISCV_RESEARCH_INTERNSHIP Public

    A hands-on program focusing on RISC-V development, including tasks from software setup to creating and demonstrating practical application using RISC V processor.

    C 6 1

  3. NASSCOM-RISC-V-based-MYTH-program NASSCOM-RISC-V-based-MYTH-program Public

    Learn digital logic design from basics to pipelines using TL-Verilog and Makerchip — fast, practical, and beginner-friendly! 🚀

    5

  4. NASSCOM-VSD-SoC-design-Program NASSCOM-VSD-SoC-design-Program Public

    In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

    10 2

  5. adarshnagrikar14/jeevayu-gsc-22 adarshnagrikar14/jeevayu-gsc-22 Public

    Jeevayu is a team project for Google solution challenge 2022.

    Dart 2

  6. DIR_V_HACKATHON DIR_V_HACKATHON Public

    DIR_V_HACKATHON

    Verilog 7 1