The standard procedure for writing Verilog code :

1. Understanding the specifications: Read and understand the system requirements, specifications, and constraints.

2. High-Level Design: Develop a high-level design of the system, including block diagram and system architecture.

3. RTL modeling: Develop RTL models for each module in the system using Verilog.

4. Testbench creation: Create a testbench to verify the RTL design and test the design for various input conditions.

5. Simulation: Run simulations to verify the RTL design and debug the RTL model.

6. Synthesis: Convert the RTL design into a gate-level representation using a synthesis tool.

7. Place and Route: Allocate the gates to physical locations on the target device and route the interconnects using a place and route tool.

8. Timing analysis: Perform a timing analysis to verify that the design meets the required timing constraints.

9. Physical verification: Check the design for any physical design rule violations.

10. Tape-out: Generate the final layout of the design and submit it for fabrication.

11. Silicon validation: Test the fabricated chip to verify it meets the specified requirements.

Note: The above steps may vary slightly depending on the design flow and the tools used, but the general idea remains the same.

Here's a Overview of Verilog with some common concepts :

1.Data types: wire, reg, integer, real, etc.

2.Module declaration: module <module_name> (<list_of_ports>);

3.Port declaration: input <port_name>, <port_name>; or output <port_name>, <port_name>;

4.Continuous assignments: assign <wire_name> = ;

5.Behavioral modeling: initial and always blocks for concurrent and sequential logic respectively.

6.Conditional statements: if (condition) begin end

7.Loops: for, while, repeat loops.

8.Case statements: case (expression) <case_item> : <case_item> : endcase

9.Function and Task: function <function_name>; <function_body> endfunction and task <task_name>; <task_body> endtask

10.Timing control: # for delaying the execution of a statement.

11.Structural modeling: instantiation of modules and use of parameter to pass values.

12.Preprocessor directives: define, include, ``ifdef, ``endif, etc.

Verilog Problems

1.Arthimatic Logic Unit(ALU)

2.Bi Directional Buffer

3.Binary to Gray Converter

4.Carry Look Ahead Adder

5.Decoder 3-8

6.Dual Port Ram

7.Encoder 3-8

8.Even Parity Generation

9.FIFO(first in first out)

10.Full Adder

11.Full Adder using Halfadder

12.Full Subtractor

13.Full Subtractor Using HalfAdder

14.Gray to Binary Converter

15.Half Adder

16.Half Subtractor

17.Melay 101&110

18.Mod11 Counter

19.Moore 101&110

20.Mux 8*1

21.Mux And Gate

22.N_bit Comparator

23.Odd-parity Generator

24.Priority Encoder 8*1

25.Ripple Carry Adder

26.Single_Port_ram

27.SR_FF