Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 615

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 222

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 333

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 846 224

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 737 178

Repositories

Showing 10 of 109 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 263 Apache-2.0 78 20 1 Updated Feb 17, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 250 Apache-2.0 31 19 29 Updated Feb 17, 2025
  • tac Public

    CHIPS Alliance Technical Advisory Council

    chipsalliance/tac’s past year of commit activity
    6 Apache-2.0 22 19 3 Updated Feb 17, 2025
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,465 222 491 (15 issues need help) 21 Updated Feb 17, 2025
  • synlig Public

    SystemVerilog synthesis tool

    chipsalliance/synlig’s past year of commit activity
    Verilog 177 Apache-2.0 23 69 10 Updated Feb 17, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 2 0 0 Updated Feb 17, 2025
  • chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 35 3 0 0 Updated Feb 17, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 14 Apache-2.0 2 12 0 Updated Feb 16, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 35 LGPL-3.0 642 0 0 Updated Feb 15, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,151 Apache-2.0 615 317 (1 issue needs help) 176 Updated Feb 15, 2025
View all repositories