coder137 · coder137 · Mar 1, 2023 · Feb 20, 2023 · Feb 20, 2023 · Feb 20, 2023
diff --git a/.github/workflows/rust_all.yml b/.github/workflows/rust_all.yml
@@ -68,3 +68,10 @@ jobs:
           cargo make ci_debug
           cargo make ci_release
           cargo doc
+
+      - name: Minimal Interrupt
+        working-directory: ${{github.workspace}}/minimal_interrupt
+        run: |
+          cargo make ci_debug
+          cargo make ci_release
+          cargo doc
diff --git a/README.md b/README.md
@@ -9,11 +9,29 @@ Rust on microcontrollers
 - Minimal buildsystem
   - Initial [cargo-make](https://github.com/sagiegurari/cargo-make) framework to have configurable build options i.e extending `cargo`
 - Minimal controller peripheral
+  - Use bindgen to transform `.c` architecture and chip files to `.rs`
   - Create `l0` and `l5` workspace layers
   - Add **architecture**, **controller** and **startup** files in `l0`
+- Minimal Drivers
+  - Write GPIO and USART drivers for high level application usage
+  - Added `l2`, `l3` and `l4` workspace layers
+  - Added **bitflags** utility library in `l2` via crates.io
+  - Added **driver interfaces**, **gpio**, **usart** drivers in `l3`
+  - Added **led** and **button** modules in `l4`
+- Minimal Interrupt
+  - Configure interrupts from high level application code
+  - Updated `l0` `l2`, `l3` and `l4` workspace layers
+  - Updated `l0` with user interrupt considerations
+  - Added **heapless** library to `l2`
+  - Added USART buffered traits to `l3`
 
 # Roadmap
 
+## Libraries
+
+- [Bitflags](https://crates.io/crates/bitflags): Rust macros to generate bitflags
+- [Heapless](https://crates.io/crates/heapless): Stack allocated data structures
+
 ## RTOS
 
 ## Debugging

diff --git a/minimal_drivers/l5/src/main.rs b/minimal_drivers/l5/src/main.rs
@@ -39,7 +39,7 @@ fn main() -> ! {
     gpiob_peripheral.configure_for_usart(GPIOAlternate::AF7, 6);
     gpiob_peripheral.configure_for_usart(GPIOAlternate::AF7, 7);
 
-    let usart1_rx_tx: &mut dyn UsartInOut = &mut USART1_PORT.take().configure_default_rx_tx();
+    let mut usart1_rx_tx = USART1_PORT.take().configure_default_rx_tx();
 
     let gpioc_peripheral = GPIOC_PORT.take();
     // Configure GPIOC port and Pin 13 as input

diff --git a/minimal_interrupt/.cargo/config.toml b/minimal_interrupt/.cargo/config.toml
@@ -0,0 +1,43 @@
+[target.thumbv7em-none-eabihf]
+# uncomment this to make `cargo run` execute programs on QEMU
+# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+rustflags = [
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  # "-C", "link-arg=--nmagic",
+
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  # "-C", "link-arg=-Tgcc_arm.ld",
+
+  # Generate a .map file
+  # "-C", "link-args=-Map=application.map",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  "-C", "linker=arm-none-eabi-gcc",
+  "-C", "link-arg=-Wl,-Tgcc_arm.ld",
+  "-C", "link-arg=-Wl,-Map,application.map",
+  "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+# target = "thumbv8m.base-none-eabi"   # Cortex-M23
+# target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
+# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)
diff --git a/minimal_interrupt/.gitignore b/minimal_interrupt/.gitignore
@@ -0,0 +1,6 @@
+# Files
+*.map
+.vscode/.cortex-debug.*
+
+# Folders
+target
diff --git a/minimal_interrupt/.vscode/launch.json b/minimal_interrupt/.vscode/launch.json
@@ -0,0 +1,36 @@
+{
+  "configurations": [
+    {
+      "cwd": "${workspaceFolder}",
+      "executable": "target/thumbv7em-none-eabihf/debug/application",
+      "configFiles": [
+        "stm32l4discovery.cfg"
+      ],
+      "postLaunchCommands": [
+        "load",
+        "monitor arm semihosting enable",
+      ],
+      "name": "Rust Debug",
+      "request": "launch",
+      "type": "cortex-debug",
+      "servertype": "openocd",
+      "svdFile": "l0/svd/STM32L4x5.svd",
+      "svdPath": "l0/svd/STM32L4x5.svd"
+    },
+    {
+      "cwd": "${workspaceFolder}",
+      "executable": "target/thumbv7em-none-eabihf/release/application",
+      "configFiles": [
+        "stm32l4discovery.cfg"
+      ],
+      "postLaunchCommands": [
+        "load",
+        "monitor arm semihosting enable",
+      ],
+      "name": "Rust Release",
+      "request": "launch",
+      "type": "cortex-debug",
+      "servertype": "openocd"
+    }
+  ]
+}
diff --git a/minimal_interrupt/.vscode/settings.json b/minimal_interrupt/.vscode/settings.json
@@ -0,0 +1,12 @@
+{
+    "rust-analyzer.cargo.target": "thumbv7em-none-eabihf",
+    "rust-analyzer.check.allTargets": false,
+    "rust-analyzer.imports.prefer.no.std": true,
+    "rust-analyzer.cargo.unsetTest": [
+        "core",
+        "l0",
+        "l3",
+        "l5",
+        "application",
+    ],
+}
diff --git a/minimal_interrupt/Cargo.toml b/minimal_interrupt/Cargo.toml
@@ -0,0 +1,7 @@
+[workspace]
+members = [
+    "l0",
+    "l3",
+    "l4",
+    "l5"
+]
diff --git a/minimal_interrupt/Makefile.toml b/minimal_interrupt/Makefile.toml
@@ -0,0 +1,87 @@
+[config]
+default_to_workspace = false
+
+# Duckscript is used here to convert \ to / for binary output path
+[tasks.build_debug]
+script_runner = "@duckscript"
+script = '''
+output = set ${CARGO_MAKE_CRATE_CUSTOM_TRIPLE_TARGET_DIRECTORY}/debug/application
+echo OUTPUT: ${output}
+output = replace ${output} \\ /
+set_env OUTPUT ${output}
+exec cargo build
+'''
+
+# Duckscript is used here to convert \ to / for binary output path
+[tasks.build_release]
+script_runner = "@duckscript"
+script = '''
+output = set ${CARGO_MAKE_CRATE_CUSTOM_TRIPLE_TARGET_DIRECTORY}/release/application
+output = replace ${output} \\ /
+set_env OUTPUT ${output}
+exec cargo build --release
+'''
+
+[tasks.test]
+command = "cargo"
+args = ["test", "--target", "${CARGO_MAKE_RUST_TARGET_TRIPLE}"]
+
+[tasks.flash_debug]
+script_runner = "@shell"
+script = '''
+openocd -f board/stm32l4discovery.cfg -c "program ${OUTPUT} verify reset exit"
+'''
+dependencies = ["build_debug"]
+
+[tasks.ci_debug]
+dependencies = [
+    "build_debug",
+    "test",
+    "objcopy_to_binary",
+    "objcopy_to_hex",
+    "objdump",
+    "size",
+]
+
+[tasks.ci_release]
+dependencies = [
+    "build_release",
+    "test",
+    "objcopy_to_binary",
+    "objcopy_to_hex",
+    "objdump",
+    "size",
+]
+
+# Private Tasks
+
+# Requires 
+# arm-none-eabi-size executable (ARM GCC toolchain)
+# OUTPUT env variable (Set by build_*)
+[tasks.size]
+private = true
+command = "arm-none-eabi-size"
+args = ["${OUTPUT}"]
+
+# arm-none-eabi-objcopy executable (ARM GCC toolchain)
+# OUTPUT env variable (Set by build_*)
+[tasks.objcopy_to_binary]
+private = true
+command = "arm-none-eabi-objcopy"
+args = ["-O", "binary", "${OUTPUT}", "${OUTPUT}.bin"]
+
+# arm-none-eabi-objcopy executable (ARM GCC toolchain)
+# OUTPUT env variable (Set by build_*)
+[tasks.objcopy_to_hex]
+private = true
+command = "arm-none-eabi-objcopy"
+args = ["-O", "ihex", "${OUTPUT}", "${OUTPUT}.hex"]
+
+# arm-none-eabi-objdump executable (ARM GCC toolchain)
+# OUTPUT env variable (Set by build_*)
+[tasks.objdump]
+private = true
+script_runner = "@shell"
+script = '''
+arm-none-eabi-objdump --source --all-headers --demangle --line-numbers --wide ${OUTPUT} > ${OUTPUT}.lst
+'''
diff --git a/minimal_interrupt/README.md b/minimal_interrupt/README.md
@@ -0,0 +1,122 @@
+- [Minimal Interrupt](#minimal-interrupt)
+  - [Links](#links)
+  - [Microcontrollers layers](#microcontrollers-layers)
+  - [Pre-requisites](#pre-requisites)
+- [Changelog](#changelog)
+  - [L0 - Entry](#l0---entry)
+  - [L0 - Utility](#l0---utility)
+  - [L0 - Chip](#l0---chip)
+  - [L0 - Architecture](#l0---architecture)
+  - [L2 - Utility](#l2---utility)
+  - [L3 Improvements](#l3-improvements)
+    - [Hardware](#hardware)
+    - [Software](#software)
+  - [L3 - Interface](#l3---interface)
+  - [L3 - Driver](#l3---driver)
+  - [L5 - Application](#l5---application)
+
+# Minimal Interrupt
+
+This code has been tested on
+
+- B-L475-IOT01A board (STM32L475VGT6 ARM Cortex M4 CPU with FPU)
+
+## Links
+
+- [Cargo binutils](https://github.com/rust-embedded/cargo-binutils)
+- [Embedded Rust book](https://doc.rust-lang.org/stable/embedded-book/)
+- [Lowlevel Embedded Rust book](https://docs.rust-embedded.org/embedonomicon/)
+
+## Microcontrollers layers
+
+- L0 Lowlevel
+  - Chip Interrupts
+- L1 RTOS
+- L2 Utility
+  - Heapless library
+- L3 Driver
+  - Interrupt support for GPIO and USART
+- L4 Sensor
+- L5 Application
+  - Interrupt usage
+
+---
+
+## Pre-requisites
+
+- Pre-requisites from `minimal_driver`
+
+# Changelog
+
+## L0 - Entry
+
+- Updated linker script to remove PROVIDE attributes
+- Updated entry point with a better EXCEPTIONS usage
+
+## L0 - Utility
+
+- Added `write_assign_register` macro
+
+## L0 - Chip
+
+- Updated `controller_init` with `SCB->VTOR = FLASH_BASE`
+- Added `attach_interrupt_handler` for STM32L475xx chip
+
+## L0 - Architecture
+
+- Added `nvic` module with `enable_irq` function
+  - NOTE, This has only been added since bindgen cannot parse `static inline` C functions
+
+
+## L2 - Utility
+
+- Added [heapless](https://crates.io/crates/heapless) library for stack based datastructures
+
+## L3 Improvements
+
+### Hardware
+
+```mermaid
+graph BT;
+  subgraph Port
+    USART1-3
+    subgraph Peripheral
+      USART
+      subgraph Register
+        CR1
+        CR2
+        RDR
+        TDR
+      end
+    end
+  end
+```
+
+### Software
+
+```mermaid
+graph BT;
+  subgraph Port
+    USART1-3
+    subgraph Peripheral
+      PolledUSART
+      BufferedUSART
+    end
+  end
+```
+
+## L3 - Interface
+
+- Removed `PeripheralConfiguration` trait
+- Added `UsartBufferedIn` and `UsartBufferedInOut` trait
+
+## L3 - Driver
+
+- Added `USARTBufferedFunction` functionality
+- Renamed to `USARTPolledFunction`
+- Renamed to `GPIOFunction`
+
+## L5 - Application
+
+- Updated example with GPIO Input using interrupt and Atomics
+- Updated example with USART Buffered RX and TX using interrupts and static stack allocated lock free queues