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tpetazzoniWolfram Sang
tpetazzoni
authored and
Wolfram Sang
committed
i2c: mv64xxx: rework offload support to fix several problems
Originally, the I2C controller supported by the i2c-mv64xxx driver requires a lot of software support: an interrupt is generated at each step of an I2C transaction (after the start bit, after sending the address, etc.) and the driver is in charge of re-programming the I2C controller to do the next step of the I2C transaction. This explains the fairly complex state machine that the driver has. On Marvell Armada XP and later processors (Armada 375, 38x, etc.), the I2C controller was extended with a part called the "I2C Bridge", which allows to offload the I2C transaction completely to the hardware. Initial support for this mechanism was added in commit 930ab3d ("i2c: mv64xxx: Add I2C Transaction Generator support"). However, the implementation done in this commit has two related issues, which this commit fixes by completely changing how the offload implementation is done: * SMBus read transfers, where there is one write to select the register immediately followed in the same transaction by one read, were making the processor hang. This was easier visible on the Marvell Armada XP WRT1900AC platform using a driver for an I2C LED controller, or on other Armada XP platforms by using a simple 'i2cget' command to read an I2C EEPROM. * The implementation was based on the fact that the offload engine was re-programmed to transfer each message of an I2C xfer: this meant that each message sent with the offload engine was starting with a normal I2C start sequence. However, the I2C subsystem assumes that all messages belonging to the same xfer will use the so-called "repeated start" so that the entire I2C xfer is seen as one transfer by the I2C devices and cannot be interrupt by other I2C masters on the same bus. In fact, the "I2C Bridge" allows to offload three types of xfer: - xfer of one write message - xfer of one read message - xfer of one write message followed by one read message For all other situations, we have to fallback to not using the "I2C Bridge" in order to get proper I2C semantics. Therefore, this commit reworks the offload implementation to put it not at the message level, but at the xfer level: in the mv64xxx_i2c_xfer() function, we decide if the transaction can be offloaded (in which case it is handled by the mv64xxx_i2c_offload_xfer() function), or otherwise it is handled by the slow path (implemented in the existing mv64xxx_i2c_execute_msg()). This allows to simplify the state machine, which no longer needs to have any state related to the offload implementation: the offload implementation is now completely separated from the slow path (with the exception of the interrupt handler, of course). In summary: - mv64xxx_i2c_can_offload() will analyze an I2C xfer and decided of the "I2C Bridge" can be used to offload it or not. - mv64xxx_i2c_offload_xfer() will actually program the "I2C Bridge" to offload one xfer (of either one or two messages), and block using mv64xxx_i2c_wait_for_completion() until the xfer completes. - The interrupt handler mv64xxx_i2c_intr() is modified to push the offload related code to a separate function, mv64xxx_i2c_intr_offload(). It will take care of reading the received data if needed. This commit was tested on: - Armada XP OpenBlocks AX3-4 (EEPROM on I2C and RTC on I2C) - Armada XP WRT1900AC (LED controller on I2C) - Armada XP GP (EEPROM on I2C) Fixes: 930ab3d ("i2c: mv64xxx: Add I2C Transaction Generator support") Cc: <stable@vger.kernel.org> # v3.12+ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [wsa: fixed checkpatch warnings] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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‎drivers/i2c/busses/i2c-mv64xxx.c

Lines changed: 186 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -75,12 +75,10 @@
7575
#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
7676
#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
7777
#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78+
#define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
7879

7980
/* Bridge Status values */
8081
#define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
81-
#define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
82-
#define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
83-
8482

8583
/* Driver states */
8684
enum {
@@ -99,14 +97,12 @@ enum {
9997
MV64XXX_I2C_ACTION_INVALID,
10098
MV64XXX_I2C_ACTION_CONTINUE,
10199
MV64XXX_I2C_ACTION_SEND_RESTART,
102-
MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
103100
MV64XXX_I2C_ACTION_SEND_ADDR_1,
104101
MV64XXX_I2C_ACTION_SEND_ADDR_2,
105102
MV64XXX_I2C_ACTION_SEND_DATA,
106103
MV64XXX_I2C_ACTION_RCV_DATA,
107104
MV64XXX_I2C_ACTION_RCV_DATA_STOP,
108105
MV64XXX_I2C_ACTION_SEND_STOP,
109-
MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
110106
};
111107

112108
struct mv64xxx_i2c_regs {
@@ -193,75 +189,6 @@ mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
193189
}
194190
}
195191

196-
static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
197-
{
198-
unsigned long data_reg_hi = 0;
199-
unsigned long data_reg_lo = 0;
200-
unsigned long ctrl_reg;
201-
struct i2c_msg *msg = drv_data->msgs;
202-
203-
if (!drv_data->offload_enabled)
204-
return -EOPNOTSUPP;
205-
206-
/* Only regular transactions can be offloaded */
207-
if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
208-
return -EINVAL;
209-
210-
/* Only 1-8 byte transfers can be offloaded */
211-
if (msg->len < 1 || msg->len > 8)
212-
return -EINVAL;
213-
214-
/* Build transaction */
215-
ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
216-
(msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
217-
218-
if ((msg->flags & I2C_M_TEN) != 0)
219-
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
220-
221-
if ((msg->flags & I2C_M_RD) == 0) {
222-
u8 local_buf[8] = { 0 };
223-
224-
memcpy(local_buf, msg->buf, msg->len);
225-
data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
226-
data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
227-
228-
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
229-
(msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
230-
231-
writel(data_reg_lo,
232-
drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
233-
writel(data_reg_hi,
234-
drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
235-
236-
} else {
237-
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
238-
(msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
239-
}
240-
241-
/* Execute transaction */
242-
writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
243-
244-
return 0;
245-
}
246-
247-
static void
248-
mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
249-
{
250-
struct i2c_msg *msg = drv_data->msg;
251-
252-
if (msg->flags & I2C_M_RD) {
253-
u32 data_reg_lo = readl(drv_data->reg_base +
254-
MV64XXX_I2C_REG_RX_DATA_LO);
255-
u32 data_reg_hi = readl(drv_data->reg_base +
256-
MV64XXX_I2C_REG_RX_DATA_HI);
257-
u8 local_buf[8] = { 0 };
258-
259-
*((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
260-
*((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
261-
memcpy(msg->buf, local_buf, msg->len);
262-
}
263-
264-
}
265192
/*
266193
*****************************************************************************
267194
*
@@ -389,16 +316,6 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
389316
drv_data->rc = -ENXIO;
390317
break;
391318

392-
case MV64XXX_I2C_STATUS_OFFLOAD_OK:
393-
if (drv_data->send_stop || drv_data->aborting) {
394-
drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
395-
drv_data->state = MV64XXX_I2C_STATE_IDLE;
396-
} else {
397-
drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
398-
drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
399-
}
400-
break;
401-
402319
default:
403320
dev_err(&drv_data->adapter.dev,
404321
"mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
@@ -419,25 +336,15 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
419336
drv_data->aborting = 0;
420337
drv_data->rc = 0;
421338

422-
/* Can we offload this msg ? */
423-
if (mv64xxx_i2c_offload_msg(drv_data) < 0) {
424-
/* No, switch to standard path */
425-
mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
426-
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
427-
drv_data->reg_base + drv_data->reg_offsets.control);
428-
}
339+
mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
340+
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
341+
drv_data->reg_base + drv_data->reg_offsets.control);
429342
}
430343

431344
static void
432345
mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
433346
{
434347
switch(drv_data->action) {
435-
case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
436-
mv64xxx_i2c_update_offload_data(drv_data);
437-
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
438-
writel(0, drv_data->reg_base +
439-
MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
440-
/* FALLTHRU */
441348
case MV64XXX_I2C_ACTION_SEND_RESTART:
442349
/* We should only get here if we have further messages */
443350
BUG_ON(drv_data->num_msgs == 0);
@@ -518,16 +425,71 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
518425
drv_data->block = 0;
519426
wake_up(&drv_data->waitq);
520427
break;
428+
}
429+
}
521430

522-
case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
523-
mv64xxx_i2c_update_offload_data(drv_data);
524-
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
525-
writel(0, drv_data->reg_base +
526-
MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
527-
drv_data->block = 0;
528-
wake_up(&drv_data->waitq);
529-
break;
431+
static void
432+
mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
433+
struct i2c_msg *msg)
434+
{
435+
u32 buf[2];
436+
437+
buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
438+
buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
439+
440+
memcpy(msg->buf, buf, msg->len);
441+
}
442+
443+
static int
444+
mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
445+
{
446+
u32 cause, status;
447+
448+
cause = readl(drv_data->reg_base +
449+
MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
450+
if (!cause)
451+
return IRQ_NONE;
452+
453+
status = readl(drv_data->reg_base +
454+
MV64XXX_I2C_REG_BRIDGE_STATUS);
455+
456+
if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
457+
drv_data->rc = -EIO;
458+
goto out;
459+
}
460+
461+
drv_data->rc = 0;
462+
463+
/*
464+
* Transaction is a one message read transaction, read data
465+
* for this message.
466+
*/
467+
if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
468+
mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
469+
drv_data->msgs++;
470+
drv_data->num_msgs--;
471+
}
472+
/*
473+
* Transaction is a two messages write/read transaction, read
474+
* data for the second (read) message.
475+
*/
476+
else if (drv_data->num_msgs == 2 &&
477+
!(drv_data->msgs[0].flags & I2C_M_RD) &&
478+
drv_data->msgs[1].flags & I2C_M_RD) {
479+
mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
480+
drv_data->msgs += 2;
481+
drv_data->num_msgs -= 2;
530482
}
483+
484+
out:
485+
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
486+
writel(0, drv_data->reg_base +
487+
MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
488+
drv_data->block = 0;
489+
490+
wake_up(&drv_data->waitq);
491+
492+
return IRQ_HANDLED;
531493
}
532494

533495
static irqreturn_t
@@ -540,20 +502,9 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
540502

541503
spin_lock_irqsave(&drv_data->lock, flags);
542504

543-
if (drv_data->offload_enabled) {
544-
while (readl(drv_data->reg_base +
545-
MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
546-
int reg_status = readl(drv_data->reg_base +
547-
MV64XXX_I2C_REG_BRIDGE_STATUS);
548-
if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
549-
status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
550-
else
551-
status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
552-
mv64xxx_i2c_fsm(drv_data, status);
553-
mv64xxx_i2c_do_action(drv_data);
554-
rc = IRQ_HANDLED;
555-
}
556-
}
505+
if (drv_data->offload_enabled)
506+
rc = mv64xxx_i2c_intr_offload(drv_data);
507+
557508
while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
558509
MV64XXX_I2C_REG_CONTROL_IFLG) {
559510
status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
@@ -635,6 +586,117 @@ mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
635586
return drv_data->rc;
636587
}
637588

589+
static void
590+
mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
591+
{
592+
struct i2c_msg *msg = drv_data->msgs;
593+
u32 buf[2];
594+
595+
memcpy(buf, msg->buf, msg->len);
596+
597+
writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
598+
writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
599+
}
600+
601+
static int
602+
mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
603+
{
604+
struct i2c_msg *msgs = drv_data->msgs;
605+
int num = drv_data->num_msgs;
606+
unsigned long ctrl_reg;
607+
unsigned long flags;
608+
609+
spin_lock_irqsave(&drv_data->lock, flags);
610+
611+
/* Build transaction */
612+
ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
613+
(msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
614+
615+
if (msgs[0].flags & I2C_M_TEN)
616+
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
617+
618+
/* Single write message transaction */
619+
if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
620+
size_t len = msgs[0].len - 1;
621+
622+
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
623+
(len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
624+
mv64xxx_i2c_prepare_tx(drv_data);
625+
}
626+
/* Single read message transaction */
627+
else if (num == 1 && msgs[0].flags & I2C_M_RD) {
628+
size_t len = msgs[0].len - 1;
629+
630+
ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
631+
(len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
632+
}
633+
/*
634+
* Transaction with one write and one read message. This is
635+
* guaranteed by the mv64xx_i2c_can_offload() checks.
636+
*/
637+
else if (num == 2) {
638+
size_t lentx = msgs[0].len - 1;
639+
size_t lenrx = msgs[1].len - 1;
640+
641+
ctrl_reg |=
642+
MV64XXX_I2C_BRIDGE_CONTROL_RD |
643+
MV64XXX_I2C_BRIDGE_CONTROL_WR |
644+
(lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
645+
(lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
646+
MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
647+
mv64xxx_i2c_prepare_tx(drv_data);
648+
}
649+
650+
/* Execute transaction */
651+
drv_data->block = 1;
652+
writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
653+
spin_unlock_irqrestore(&drv_data->lock, flags);
654+
655+
mv64xxx_i2c_wait_for_completion(drv_data);
656+
657+
return drv_data->rc;
658+
}
659+
660+
static bool
661+
mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
662+
{
663+
return msg->len <= 8 && msg->len >= 1;
664+
}
665+
666+
static bool
667+
mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
668+
{
669+
struct i2c_msg *msgs = drv_data->msgs;
670+
int num = drv_data->num_msgs;
671+
672+
return false;
673+
674+
if (!drv_data->offload_enabled)
675+
return false;
676+
677+
/*
678+
* We can offload a transaction consisting of a single
679+
* message, as long as the message has a length between 1 and
680+
* 8 bytes.
681+
*/
682+
if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
683+
return true;
684+
685+
/*
686+
* We can offload a transaction consisting of two messages, if
687+
* the first is a write and a second is a read, and both have
688+
* a length between 1 and 8 bytes.
689+
*/
690+
if (num == 2 &&
691+
mv64xxx_i2c_valid_offload_sz(msgs) &&
692+
mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
693+
!(msgs[0].flags & I2C_M_RD) &&
694+
msgs[1].flags & I2C_M_RD)
695+
return true;
696+
697+
return false;
698+
}
699+
638700
/*
639701
*****************************************************************************
640702
*
@@ -658,7 +720,11 @@ mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
658720
drv_data->msgs = msgs;
659721
drv_data->num_msgs = num;
660722

661-
rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
723+
if (mv64xxx_i2c_can_offload(drv_data))
724+
rc = mv64xxx_i2c_offload_xfer(drv_data);
725+
else
726+
rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
727+
662728
if (rc < 0)
663729
ret = rc;
664730

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