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dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the numbering right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and all the following ids are updated accordingly. Reported-by: Patrick Wildt <patrick@blueri.se> Fixes: 1cf3817 ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎include/dt-bindings/clock/imx8mq-clock.h

Lines changed: 110 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -245,160 +245,160 @@
245245
/* USB_CORE_REF */
246246
#define IMX8MQ_CLK_USB_CORE_REF 152
247247
/* USB_PHY_REF */
248-
#define IMX8MQ_CLK_USB_PHY_REF 163
248+
#define IMX8MQ_CLK_USB_PHY_REF 153
249249
/* ECSPI1 */
250-
#define IMX8MQ_CLK_ECSPI1 164
250+
#define IMX8MQ_CLK_ECSPI1 154
251251
/* ECSPI2 */
252-
#define IMX8MQ_CLK_ECSPI2 165
252+
#define IMX8MQ_CLK_ECSPI2 155
253253
/* PWM1 */
254-
#define IMX8MQ_CLK_PWM1 166
254+
#define IMX8MQ_CLK_PWM1 156
255255
/* PWM2 */
256-
#define IMX8MQ_CLK_PWM2 167
256+
#define IMX8MQ_CLK_PWM2 157
257257
/* PWM3 */
258-
#define IMX8MQ_CLK_PWM3 168
258+
#define IMX8MQ_CLK_PWM3 158
259259
/* PWM4 */
260-
#define IMX8MQ_CLK_PWM4 169
260+
#define IMX8MQ_CLK_PWM4 159
261261
/* GPT1 */
262-
#define IMX8MQ_CLK_GPT1 170
262+
#define IMX8MQ_CLK_GPT1 160
263263
/* WDOG */
264-
#define IMX8MQ_CLK_WDOG 171
264+
#define IMX8MQ_CLK_WDOG 161
265265
/* WRCLK */
266-
#define IMX8MQ_CLK_WRCLK 172
266+
#define IMX8MQ_CLK_WRCLK 162
267267
/* DSI_CORE */
268-
#define IMX8MQ_CLK_DSI_CORE 173
268+
#define IMX8MQ_CLK_DSI_CORE 163
269269
/* DSI_PHY */
270-
#define IMX8MQ_CLK_DSI_PHY_REF 174
270+
#define IMX8MQ_CLK_DSI_PHY_REF 164
271271
/* DSI_DBI */
272-
#define IMX8MQ_CLK_DSI_DBI 175
272+
#define IMX8MQ_CLK_DSI_DBI 165
273273
/*DSI_ESC */
274-
#define IMX8MQ_CLK_DSI_ESC 176
274+
#define IMX8MQ_CLK_DSI_ESC 166
275275
/* CSI1_CORE */
276-
#define IMX8MQ_CLK_CSI1_CORE 177
276+
#define IMX8MQ_CLK_CSI1_CORE 167
277277
/* CSI1_PHY */
278-
#define IMX8MQ_CLK_CSI1_PHY_REF 178
278+
#define IMX8MQ_CLK_CSI1_PHY_REF 168
279279
/* CSI_ESC */
280-
#define IMX8MQ_CLK_CSI1_ESC 179
280+
#define IMX8MQ_CLK_CSI1_ESC 169
281281
/* CSI2_CORE */
282282
#define IMX8MQ_CLK_CSI2_CORE 170
283283
/* CSI2_PHY */
284-
#define IMX8MQ_CLK_CSI2_PHY_REF 181
284+
#define IMX8MQ_CLK_CSI2_PHY_REF 171
285285
/* CSI2_ESC */
286-
#define IMX8MQ_CLK_CSI2_ESC 182
286+
#define IMX8MQ_CLK_CSI2_ESC 172
287287
/* PCIE2_CTRL */
288-
#define IMX8MQ_CLK_PCIE2_CTRL 183
288+
#define IMX8MQ_CLK_PCIE2_CTRL 173
289289
/* PCIE2_PHY */
290-
#define IMX8MQ_CLK_PCIE2_PHY 184
290+
#define IMX8MQ_CLK_PCIE2_PHY 174
291291
/* PCIE2_AUX */
292-
#define IMX8MQ_CLK_PCIE2_AUX 185
292+
#define IMX8MQ_CLK_PCIE2_AUX 175
293293
/* ECSPI3 */
294-
#define IMX8MQ_CLK_ECSPI3 186
294+
#define IMX8MQ_CLK_ECSPI3 176
295295

296296
/* CCGR clocks */
297-
#define IMX8MQ_CLK_A53_ROOT 187
298-
#define IMX8MQ_CLK_DRAM_ROOT 188
299-
#define IMX8MQ_CLK_ECSPI1_ROOT 189
297+
#define IMX8MQ_CLK_A53_ROOT 177
298+
#define IMX8MQ_CLK_DRAM_ROOT 178
299+
#define IMX8MQ_CLK_ECSPI1_ROOT 179
300300
#define IMX8MQ_CLK_ECSPI2_ROOT 180
301301
#define IMX8MQ_CLK_ECSPI3_ROOT 181
302302
#define IMX8MQ_CLK_ENET1_ROOT 182
303-
#define IMX8MQ_CLK_GPT1_ROOT 193
304-
#define IMX8MQ_CLK_I2C1_ROOT 194
305-
#define IMX8MQ_CLK_I2C2_ROOT 195
306-
#define IMX8MQ_CLK_I2C3_ROOT 196
307-
#define IMX8MQ_CLK_I2C4_ROOT 197
308-
#define IMX8MQ_CLK_M4_ROOT 198
309-
#define IMX8MQ_CLK_PCIE1_ROOT 199
310-
#define IMX8MQ_CLK_PCIE2_ROOT 200
311-
#define IMX8MQ_CLK_PWM1_ROOT 201
312-
#define IMX8MQ_CLK_PWM2_ROOT 202
313-
#define IMX8MQ_CLK_PWM3_ROOT 203
314-
#define IMX8MQ_CLK_PWM4_ROOT 204
315-
#define IMX8MQ_CLK_QSPI_ROOT 205
316-
#define IMX8MQ_CLK_SAI1_ROOT 206
317-
#define IMX8MQ_CLK_SAI2_ROOT 207
318-
#define IMX8MQ_CLK_SAI3_ROOT 208
319-
#define IMX8MQ_CLK_SAI4_ROOT 209
320-
#define IMX8MQ_CLK_SAI5_ROOT 210
321-
#define IMX8MQ_CLK_SAI6_ROOT 212
322-
#define IMX8MQ_CLK_UART1_ROOT 213
323-
#define IMX8MQ_CLK_UART2_ROOT 214
324-
#define IMX8MQ_CLK_UART3_ROOT 215
325-
#define IMX8MQ_CLK_UART4_ROOT 216
326-
#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
327-
#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
328-
#define IMX8MQ_CLK_USB1_PHY_ROOT 219
329-
#define IMX8MQ_CLK_USB2_PHY_ROOT 220
330-
#define IMX8MQ_CLK_USDHC1_ROOT 221
331-
#define IMX8MQ_CLK_USDHC2_ROOT 222
332-
#define IMX8MQ_CLK_WDOG1_ROOT 223
333-
#define IMX8MQ_CLK_WDOG2_ROOT 224
334-
#define IMX8MQ_CLK_WDOG3_ROOT 225
335-
#define IMX8MQ_CLK_GPU_ROOT 226
336-
#define IMX8MQ_CLK_HEVC_ROOT 227
337-
#define IMX8MQ_CLK_AVC_ROOT 228
338-
#define IMX8MQ_CLK_VP9_ROOT 229
339-
#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
340-
#define IMX8MQ_CLK_DISP_ROOT 231
341-
#define IMX8MQ_CLK_HDMI_ROOT 232
342-
#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
343-
#define IMX8MQ_CLK_VPU_DEC_ROOT 234
344-
#define IMX8MQ_CLK_CSI1_ROOT 235
345-
#define IMX8MQ_CLK_CSI2_ROOT 236
346-
#define IMX8MQ_CLK_RAWNAND_ROOT 237
347-
#define IMX8MQ_CLK_SDMA1_ROOT 238
348-
#define IMX8MQ_CLK_SDMA2_ROOT 239
349-
#define IMX8MQ_CLK_VPU_G1_ROOT 240
350-
#define IMX8MQ_CLK_VPU_G2_ROOT 241
303+
#define IMX8MQ_CLK_GPT1_ROOT 183
304+
#define IMX8MQ_CLK_I2C1_ROOT 184
305+
#define IMX8MQ_CLK_I2C2_ROOT 185
306+
#define IMX8MQ_CLK_I2C3_ROOT 186
307+
#define IMX8MQ_CLK_I2C4_ROOT 187
308+
#define IMX8MQ_CLK_M4_ROOT 188
309+
#define IMX8MQ_CLK_PCIE1_ROOT 189
310+
#define IMX8MQ_CLK_PCIE2_ROOT 190
311+
#define IMX8MQ_CLK_PWM1_ROOT 191
312+
#define IMX8MQ_CLK_PWM2_ROOT 192
313+
#define IMX8MQ_CLK_PWM3_ROOT 193
314+
#define IMX8MQ_CLK_PWM4_ROOT 194
315+
#define IMX8MQ_CLK_QSPI_ROOT 195
316+
#define IMX8MQ_CLK_SAI1_ROOT 196
317+
#define IMX8MQ_CLK_SAI2_ROOT 197
318+
#define IMX8MQ_CLK_SAI3_ROOT 198
319+
#define IMX8MQ_CLK_SAI4_ROOT 199
320+
#define IMX8MQ_CLK_SAI5_ROOT 200
321+
#define IMX8MQ_CLK_SAI6_ROOT 201
322+
#define IMX8MQ_CLK_UART1_ROOT 202
323+
#define IMX8MQ_CLK_UART2_ROOT 203
324+
#define IMX8MQ_CLK_UART3_ROOT 204
325+
#define IMX8MQ_CLK_UART4_ROOT 205
326+
#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
327+
#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
328+
#define IMX8MQ_CLK_USB1_PHY_ROOT 208
329+
#define IMX8MQ_CLK_USB2_PHY_ROOT 209
330+
#define IMX8MQ_CLK_USDHC1_ROOT 210
331+
#define IMX8MQ_CLK_USDHC2_ROOT 211
332+
#define IMX8MQ_CLK_WDOG1_ROOT 212
333+
#define IMX8MQ_CLK_WDOG2_ROOT 213
334+
#define IMX8MQ_CLK_WDOG3_ROOT 214
335+
#define IMX8MQ_CLK_GPU_ROOT 215
336+
#define IMX8MQ_CLK_HEVC_ROOT 216
337+
#define IMX8MQ_CLK_AVC_ROOT 217
338+
#define IMX8MQ_CLK_VP9_ROOT 218
339+
#define IMX8MQ_CLK_HEVC_INTER_ROOT 219
340+
#define IMX8MQ_CLK_DISP_ROOT 220
341+
#define IMX8MQ_CLK_HDMI_ROOT 221
342+
#define IMX8MQ_CLK_HDMI_PHY_ROOT 222
343+
#define IMX8MQ_CLK_VPU_DEC_ROOT 223
344+
#define IMX8MQ_CLK_CSI1_ROOT 224
345+
#define IMX8MQ_CLK_CSI2_ROOT 225
346+
#define IMX8MQ_CLK_RAWNAND_ROOT 226
347+
#define IMX8MQ_CLK_SDMA1_ROOT 227
348+
#define IMX8MQ_CLK_SDMA2_ROOT 228
349+
#define IMX8MQ_CLK_VPU_G1_ROOT 229
350+
#define IMX8MQ_CLK_VPU_G2_ROOT 230
351351

352352
/* SCCG PLL GATE */
353-
#define IMX8MQ_SYS1_PLL_OUT 242
354-
#define IMX8MQ_SYS2_PLL_OUT 243
355-
#define IMX8MQ_SYS3_PLL_OUT 244
356-
#define IMX8MQ_DRAM_PLL_OUT 245
357-
358-
#define IMX8MQ_GPT_3M_CLK 246
359-
360-
#define IMX8MQ_CLK_IPG_ROOT 247
361-
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
362-
#define IMX8MQ_CLK_SAI1_IPG 249
363-
#define IMX8MQ_CLK_SAI2_IPG 250
364-
#define IMX8MQ_CLK_SAI3_IPG 251
365-
#define IMX8MQ_CLK_SAI4_IPG 252
366-
#define IMX8MQ_CLK_SAI5_IPG 253
367-
#define IMX8MQ_CLK_SAI6_IPG 254
353+
#define IMX8MQ_SYS1_PLL_OUT 231
354+
#define IMX8MQ_SYS2_PLL_OUT 232
355+
#define IMX8MQ_SYS3_PLL_OUT 233
356+
#define IMX8MQ_DRAM_PLL_OUT 234
357+
358+
#define IMX8MQ_GPT_3M_CLK 235
359+
360+
#define IMX8MQ_CLK_IPG_ROOT 236
361+
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
362+
#define IMX8MQ_CLK_SAI1_IPG 238
363+
#define IMX8MQ_CLK_SAI2_IPG 239
364+
#define IMX8MQ_CLK_SAI3_IPG 240
365+
#define IMX8MQ_CLK_SAI4_IPG 241
366+
#define IMX8MQ_CLK_SAI5_IPG 242
367+
#define IMX8MQ_CLK_SAI6_IPG 243
368368

369369
/* DSI AHB/IPG clocks */
370370
/* rxesc clock */
371-
#define IMX8MQ_CLK_DSI_AHB 255
371+
#define IMX8MQ_CLK_DSI_AHB 244
372372
/* txesc clock */
373-
#define IMX8MQ_CLK_DSI_IPG_DIV 256
373+
#define IMX8MQ_CLK_DSI_IPG_DIV 245
374374

375-
#define IMX8MQ_CLK_TMU_ROOT 257
375+
#define IMX8MQ_CLK_TMU_ROOT 246
376376

377377
/* Display root clocks */
378-
#define IMX8MQ_CLK_DISP_AXI_ROOT 258
379-
#define IMX8MQ_CLK_DISP_APB_ROOT 259
380-
#define IMX8MQ_CLK_DISP_RTRM_ROOT 260
378+
#define IMX8MQ_CLK_DISP_AXI_ROOT 247
379+
#define IMX8MQ_CLK_DISP_APB_ROOT 248
380+
#define IMX8MQ_CLK_DISP_RTRM_ROOT 249
381381

382-
#define IMX8MQ_CLK_OCOTP_ROOT 261
382+
#define IMX8MQ_CLK_OCOTP_ROOT 250
383383

384-
#define IMX8MQ_CLK_DRAM_ALT_ROOT 262
385-
#define IMX8MQ_CLK_DRAM_CORE 263
384+
#define IMX8MQ_CLK_DRAM_ALT_ROOT 251
385+
#define IMX8MQ_CLK_DRAM_CORE 252
386386

387-
#define IMX8MQ_CLK_MU_ROOT 264
388-
#define IMX8MQ_VIDEO2_PLL_OUT 265
387+
#define IMX8MQ_CLK_MU_ROOT 253
388+
#define IMX8MQ_VIDEO2_PLL_OUT 254
389389

390-
#define IMX8MQ_CLK_CLKO2 266
390+
#define IMX8MQ_CLK_CLKO2 255
391391

392-
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 267
392+
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
393393

394-
#define IMX8MQ_CLK_CLKO1 268
395-
#define IMX8MQ_CLK_ARM 269
394+
#define IMX8MQ_CLK_CLKO1 257
395+
#define IMX8MQ_CLK_ARM 258
396396

397-
#define IMX8MQ_CLK_GPIO1_ROOT 270
398-
#define IMX8MQ_CLK_GPIO2_ROOT 271
399-
#define IMX8MQ_CLK_GPIO3_ROOT 272
400-
#define IMX8MQ_CLK_GPIO4_ROOT 273
401-
#define IMX8MQ_CLK_GPIO5_ROOT 274
397+
#define IMX8MQ_CLK_GPIO1_ROOT 259
398+
#define IMX8MQ_CLK_GPIO2_ROOT 260
399+
#define IMX8MQ_CLK_GPIO3_ROOT 261
400+
#define IMX8MQ_CLK_GPIO4_ROOT 262
401+
#define IMX8MQ_CLK_GPIO5_ROOT 263
402402

403-
#define IMX8MQ_CLK_END 275
403+
#define IMX8MQ_CLK_END 264
404404
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */

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