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kliang2Ingo Molnar
kliang2
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Ingo Molnar
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perf/x86/intel/uncore: Add Broadwell-DE uncore support
The uncore subsystem for Broadwell-DE is similar to Haswell-EP. There are some differences in pci device IDs, box number and constraints. Please refer to the public document: http://www.intel.com/content/www/us/en/processors/xeon/xeon-d-1500-uncore-performance-monitoring.html Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1435839172-15114-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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‎arch/x86/kernel/cpu/perf_event_intel_uncore.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -911,6 +911,9 @@ static int __init uncore_pci_init(void)
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case 63: /* Haswell-EP */
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ret = hswep_uncore_pci_init();
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break;
914+
case 86: /* BDX-DE */
915+
ret = bdx_uncore_pci_init();
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break;
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case 42: /* Sandy Bridge */
915918
ret = snb_uncore_pci_init();
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break;
@@ -1229,6 +1232,9 @@ static int __init uncore_cpu_init(void)
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case 63: /* Haswell-EP */
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hswep_uncore_cpu_init();
12311234
break;
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case 86: /* BDX-DE */
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bdx_uncore_cpu_init();
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break;
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default:
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return 0;
12341240
}

‎arch/x86/kernel/cpu/perf_event_intel_uncore.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,8 @@ int ivbep_uncore_pci_init(void);
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void ivbep_uncore_cpu_init(void);
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int hswep_uncore_pci_init(void);
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void hswep_uncore_cpu_init(void);
339+
int bdx_uncore_pci_init(void);
340+
void bdx_uncore_cpu_init(void);
339341

340342
/* perf_event_intel_uncore_nhmex.c */
341343
void nhmex_uncore_cpu_init(void);

‎arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c

Lines changed: 164 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2321,3 +2321,167 @@ int hswep_uncore_pci_init(void)
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return 0;
23222322
}
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/* end of Haswell-EP uncore support */
2324+
2325+
/* BDX-DE uncore support */
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2327+
static struct intel_uncore_type bdx_uncore_ubox = {
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.name = "ubox",
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.num_counters = 2,
2330+
.num_boxes = 1,
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.perf_ctr_bits = 48,
2332+
.fixed_ctr_bits = 48,
2333+
.perf_ctr = HSWEP_U_MSR_PMON_CTR0,
2334+
.event_ctl = HSWEP_U_MSR_PMON_CTL0,
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.event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
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.fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
2337+
.fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
2338+
.num_shared_regs = 1,
2339+
.ops = &ivbep_uncore_msr_ops,
2340+
.format_group = &ivbep_uncore_ubox_format_group,
2341+
};
2342+
2343+
static struct event_constraint bdx_uncore_cbox_constraints[] = {
2344+
UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2346+
UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
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EVENT_CONSTRAINT_END
2348+
};
2349+
2350+
static struct intel_uncore_type bdx_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.perf_ctr_bits = 48,
2355+
.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
2356+
.perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
2357+
.event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
2358+
.box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
2359+
.msr_offset = HSWEP_CBO_MSR_OFFSET,
2360+
.num_shared_regs = 1,
2361+
.constraints = bdx_uncore_cbox_constraints,
2362+
.ops = &hswep_uncore_cbox_ops,
2363+
.format_group = &hswep_uncore_cbox_format_group,
2364+
};
2365+
2366+
static struct intel_uncore_type *bdx_msr_uncores[] = {
2367+
&bdx_uncore_ubox,
2368+
&bdx_uncore_cbox,
2369+
&hswep_uncore_pcu,
2370+
NULL,
2371+
};
2372+
2373+
void bdx_uncore_cpu_init(void)
2374+
{
2375+
if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2376+
bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
2377+
uncore_msr_uncores = bdx_msr_uncores;
2378+
}
2379+
2380+
static struct intel_uncore_type bdx_uncore_ha = {
2381+
.name = "ha",
2382+
.num_counters = 4,
2383+
.num_boxes = 1,
2384+
.perf_ctr_bits = 48,
2385+
SNBEP_UNCORE_PCI_COMMON_INIT(),
2386+
};
2387+
2388+
static struct intel_uncore_type bdx_uncore_imc = {
2389+
.name = "imc",
2390+
.num_counters = 5,
2391+
.num_boxes = 2,
2392+
.perf_ctr_bits = 48,
2393+
.fixed_ctr_bits = 48,
2394+
.fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
2395+
.fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
2396+
.event_descs = hswep_uncore_imc_events,
2397+
SNBEP_UNCORE_PCI_COMMON_INIT(),
2398+
};
2399+
2400+
static struct intel_uncore_type bdx_uncore_irp = {
2401+
.name = "irp",
2402+
.num_counters = 4,
2403+
.num_boxes = 1,
2404+
.perf_ctr_bits = 48,
2405+
.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2406+
.box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2407+
.ops = &hswep_uncore_irp_ops,
2408+
.format_group = &snbep_uncore_format_group,
2409+
};
2410+
2411+
2412+
static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
2413+
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2414+
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2415+
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2416+
UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
2417+
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
2418+
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2419+
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2420+
EVENT_CONSTRAINT_END
2421+
};
2422+
2423+
static struct intel_uncore_type bdx_uncore_r2pcie = {
2424+
.name = "r2pcie",
2425+
.num_counters = 4,
2426+
.num_boxes = 1,
2427+
.perf_ctr_bits = 48,
2428+
.constraints = bdx_uncore_r2pcie_constraints,
2429+
SNBEP_UNCORE_PCI_COMMON_INIT(),
2430+
};
2431+
2432+
enum {
2433+
BDX_PCI_UNCORE_HA,
2434+
BDX_PCI_UNCORE_IMC,
2435+
BDX_PCI_UNCORE_IRP,
2436+
BDX_PCI_UNCORE_R2PCIE,
2437+
};
2438+
2439+
static struct intel_uncore_type *bdx_pci_uncores[] = {
2440+
[BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
2441+
[BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
2442+
[BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
2443+
[BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
2444+
NULL,
2445+
};
2446+
2447+
static DEFINE_PCI_DEVICE_TABLE(bdx_uncore_pci_ids) = {
2448+
{ /* Home Agent 0 */
2449+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
2450+
.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
2451+
},
2452+
{ /* MC0 Channel 0 */
2453+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
2454+
.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
2455+
},
2456+
{ /* MC0 Channel 1 */
2457+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
2458+
.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
2459+
},
2460+
{ /* IRP */
2461+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
2462+
.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
2463+
},
2464+
{ /* R2PCIe */
2465+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
2466+
.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
2467+
},
2468+
{ /* end: all zeroes */ }
2469+
};
2470+
2471+
static struct pci_driver bdx_uncore_pci_driver = {
2472+
.name = "bdx_uncore",
2473+
.id_table = bdx_uncore_pci_ids,
2474+
};
2475+
2476+
int bdx_uncore_pci_init(void)
2477+
{
2478+
int ret = snbep_pci2phy_map_init(0x6f1e);
2479+
2480+
if (ret)
2481+
return ret;
2482+
uncore_pci_uncores = bdx_pci_uncores;
2483+
uncore_pci_driver = &bdx_uncore_pci_driver;
2484+
return 0;
2485+
}
2486+
2487+
/* end of BDX-DE uncore support */

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