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Merge tag 'drm-misc-next-2018-04-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v4.18: UAPI Changes: - Add support for a generic plane alpha property to sun4i, rcar-du and atmel-hclcdc. (Maxime) Core Changes: - Stop looking at legacy plane->fb and crtc members in atomic drivers. (Ville) - mode_valid return type fixes. (Luc) - Handle zpos normalization in the core. (Peter) Driver Changes: - Implement CTM, plane alpha and generic async cursor support in vc4. (Stefan) - Various fixes for HPD and aux chan in drm_bridge/analogix_dp. (Lin, Zain, Douglas) - Add support for MIPI DSI to sun4i. (Maxime) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Thu 26 Apr 2018 08:21:01 PM AEST # gpg: using RSA key FE558C72A67013C3 # gpg: Can't check signature: public key not found Link: https://patchwork.freedesktop.org/patch/msgid/b33da7eb-efc9-ae6f-6f69-b7acd6df6797@mblankhorst.nl
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‎Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt

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@@ -14,7 +14,13 @@ Required properties:
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"adi,adv7513"
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"adi,adv7533"
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- reg: I2C slave address
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- reg: I2C slave addresses
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The ADV7511 internal registers are split into four pages exposed through
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different I2C addresses, creating four register maps. Each map has it own
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I2C address and acts as a standard slave device on the I2C bus. The main
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address is mandatory, others are optional and revert to defaults if not
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specified.
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The ADV7511 supports a large number of input data formats that differ by their
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color depth, color format, clock mode, bit justification and random
@@ -70,6 +76,9 @@ Optional properties:
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rather than generate its own timings for HDMI output.
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- clocks: from common clock binding: reference to the CEC clock.
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- clock-names: from common clock binding: must be "cec".
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- reg-names : Names of maps with programmable addresses.
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It can contain any map needing a non-default address.
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Possible maps names are : "main", "edid", "cec", "packet"
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Required nodes:
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@@ -88,7 +97,12 @@ Example
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adv7511w: hdmi@39 {
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compatible = "adi,adv7511w";
91-
reg = <39>;
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/*
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* The EDID page will be accessible on address 0x66 on the I2C
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* bus. All other maps continue to use their default addresses.
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*/
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reg = <0x39>, <0x66>;
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reg-names = "main", "edid";
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interrupt-parent = <&gpio3>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
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clocks = <&cec_clock>;

‎Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt

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Cadence DSI bridge
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==================
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The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
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6+
Required properties:
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- compatible: should be set to "cdns,dsi".
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- reg: physical base address and length of the controller's registers.
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- interrupts: interrupt line connected to the DSI bridge.
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- clocks: DSI bridge clocks.
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- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
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- phys: phandle link to the MIPI D-PHY controller.
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- phy-names: must contain "dphy".
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- #address-cells: must be set to 1.
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- #size-cells: must be set to 0.
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Optional properties:
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- resets: DSI reset lines.
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- reset-names: can contain "dsi_p_rst".
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Required subnodes:
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- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
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2 ports are available:
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* port 0: this port is only needed if some of your DSI devices are
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controlled through an external bus like I2C or SPI. Can have at
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most 4 endpoints. The endpoint number is directly encoding the
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DSI virtual channel used by this device.
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* port 1: represents the DPI input.
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Other ports will be added later to support the new kind of inputs.
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- one subnode per DSI device connected on the DSI bus. Each DSI device should
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contain a reg property encoding its virtual channel.
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Cadence DPHY
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============
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Cadence DPHY block.
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Required properties:
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- compatible: should be set to "cdns,dphy".
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- reg: physical base address and length of the DPHY registers.
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- clocks: DPHY reference clocks.
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- clock-names: must contain "psm" and "pll_ref".
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- #phy-cells: must be set to 0.
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Example:
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dphy0: dphy@fd0e0000{
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compatible = "cdns,dphy";
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reg = <0x0 0xfd0e0000 0x0 0x1000>;
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clocks = <&psm_clk>, <&pll_ref_clk>;
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clock-names = "psm", "pll_ref";
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#phy-cells = <0>;
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};
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
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phys = <&dphy0>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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67+
ports {
68+
#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
72+
reg = <1>;
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dsi0_dpi_input: endpoint {
74+
remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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panel: dsi-dev@0 {
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compatible = "<vendor,panel>";
81+
reg = <0>;
82+
};
83+
};
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or
86+
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dsi0: dsi@fd0c0000 {
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compatible = "cdns,dsi";
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reg = <0x0 0xfd0c0000 0x0 0x1000>;
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clocks = <&pclk>, <&sysclk>;
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clock-names = "dsi_p_clk", "dsi_sys_clk";
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interrupts = <1>;
93+
phys = <&dphy1>;
94+
phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_panel_input>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_dpi_input: endpoint {
116+
remote-endpoint = <&xxx_dpi_output>;
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};
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};
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};
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};
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i2c@xxx {
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panel: panel@59 {
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compatible = "<vendor,panel>";
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reg = <0x59>;
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port {
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dsi_panel_input: endpoint {
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remote-endpoint = <&dsi0_output>;
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};
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};
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};
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};

‎Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt

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Thine Electronics THC63LVD1024 LVDS decoder
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-------------------------------------------
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The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
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to parallel data outputs. The chip supports single/dual input/output modes,
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handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
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Single or dual operation mode, output data mapping and DDR output modes are
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configured through input signals and the chip does not expose any control bus.
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Required properties:
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- compatible: Shall be "thine,thc63lvd1024"
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- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
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PPL and digital circuitry
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16+
Optional properties:
17+
- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
18+
- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
19+
20+
The THC63LVD1024 video port connections are modeled according
21+
to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
22+
23+
Required video port nodes:
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- port@0: First LVDS input port
25+
- port@2: First digital CMOS/TTL parallel output
26+
27+
Optional video port nodes:
28+
- port@1: Second LVDS input port
29+
- port@3: Second digital CMOS/TTL parallel output
30+
31+
Example:
32+
--------
33+
34+
thc63lvd1024: lvds-decoder {
35+
compatible = "thine,thc63lvd1024";
36+
37+
vcc-supply = <&reg_lvds_vcc>;
38+
powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
39+
40+
ports {
41+
#address-cells = <1>;
42+
#size-cells = <0>;
43+
44+
port@0 {
45+
reg = <0>;
46+
47+
lvds_dec_in_0: endpoint {
48+
remote-endpoint = <&lvds_out>;
49+
};
50+
};
51+
52+
port@2{
53+
reg = <2>;
54+
55+
lvds_dec_out_2: endpoint {
56+
remote-endpoint = <&adv7511_in>;
57+
};
58+
};
59+
};
60+
};

‎Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt

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1+
Allwinner A31 DSI Encoder
2+
=========================
3+
4+
The DSI pipeline consists of two separate blocks: the DSI controller
5+
itself, and its associated D-PHY.
6+
7+
DSI Encoder
8+
-----------
9+
10+
The DSI Encoder generates the DSI signal from the TCON's.
11+
12+
Required properties:
13+
- compatible: value must be one of:
14+
* allwinner,sun6i-a31-mipi-dsi
15+
- reg: base address and size of memory-mapped region
16+
- interrupts: interrupt associated to this IP
17+
- clocks: phandles to the clocks feeding the DSI encoder
18+
* bus: the DSI interface clock
19+
* mod: the DSI module clock
20+
- clock-names: the clock names mentioned above
21+
- phys: phandle to the D-PHY
22+
- phy-names: must be "dphy"
23+
- resets: phandle to the reset controller driving the encoder
24+
25+
- ports: A ports node with endpoint definitions as defined in
26+
Documentation/devicetree/bindings/media/video-interfaces.txt. The
27+
first port should be the input endpoint, usually coming from the
28+
associated TCON.
29+
30+
Any MIPI-DSI device attached to this should be described according to
31+
the bindings defined in ../mipi-dsi-bus.txt
32+
33+
D-PHY
34+
-----
35+
36+
Required properties:
37+
- compatible: value must be one of:
38+
* allwinner,sun6i-a31-mipi-dphy
39+
- reg: base address and size of memory-mapped region
40+
- clocks: phandles to the clocks feeding the DSI encoder
41+
* bus: the DSI interface clock
42+
* mod: the DSI module clock
43+
- clock-names: the clock names mentioned above
44+
- resets: phandle to the reset controller driving the encoder
45+
46+
Example:
47+
48+
dsi0: dsi@1ca0000 {
49+
compatible = "allwinner,sun6i-a31-mipi-dsi";
50+
reg = <0x01ca0000 0x1000>;
51+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
52+
clocks = <&ccu CLK_BUS_MIPI_DSI>,
53+
<&ccu CLK_DSI_SCLK>;
54+
clock-names = "bus", "mod";
55+
resets = <&ccu RST_BUS_MIPI_DSI>;
56+
phys = <&dphy0>;
57+
phy-names = "dphy";
58+
#address-cells = <1>;
59+
#size-cells = <0>;
60+
61+
panel@0 {
62+
compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
63+
reg = <0>;
64+
power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
65+
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
66+
backlight = <&pwm_bl>;
67+
};
68+
69+
ports {
70+
#address-cells = <1>;
71+
#size-cells = <0>;
72+
73+
port@0 {
74+
#address-cells = <1>;
75+
#size-cells = <0>;
76+
reg = <0>;
77+
78+
dsi0_in_tcon0: endpoint {
79+
remote-endpoint = <&tcon0_out_dsi0>;
80+
};
81+
};
82+
};
83+
};
84+
85+
dphy0: d-phy@1ca1000 {
86+
compatible = "allwinner,sun6i-a31-mipi-dphy";
87+
reg = <0x01ca1000 0x1000>;
88+
clocks = <&ccu CLK_BUS_MIPI_DSI>,
89+
<&ccu CLK_DSI_DPHY>;
90+
clock-names = "bus", "mod";
91+
resets = <&ccu RST_BUS_MIPI_DSI>;
92+
#phy-cells = <0>;
93+
};

‎Documentation/gpu/drivers.rst

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@@ -12,6 +12,7 @@ GPU Driver Documentation
1212
tve200
1313
vc4
1414
bridge/dw-hdmi
15+
xen-front
1516

1617
.. only:: subproject and html
1718

‎Documentation/gpu/kms-properties.csv

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@@ -98,5 +98,4 @@ radeon,DVI-I,“coherent”,RANGE,"Min=0, Max=1",Connector,TBD
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,,"""underscan vborder""",RANGE,"Min=0, Max=128",Connector,TBD
9999
,Audio,“audio”,ENUM,"{ ""off"", ""on"", ""auto"" }",Connector,TBD
100100
,FMT Dithering,“dither”,ENUM,"{ ""off"", ""on"" }",Connector,TBD
101-
rcar-du,Generic,"""alpha""",RANGE,"Min=0, Max=255",Plane,TBD
102101
,,"""colorkey""",RANGE,"Min=0, Max=0x01ffffff",Plane,TBD

‎Documentation/gpu/todo.rst

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@@ -212,6 +212,24 @@ probably use drm_fb_helper_fbdev_teardown().
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213213
Contact: Maintainer of the driver you plan to convert
214214

215+
Clean up mmap forwarding
216+
------------------------
217+
218+
A lot of drivers forward gem mmap calls to dma-buf mmap for imported buffers.
219+
And also a lot of them forward dma-buf mmap to the gem mmap implementations.
220+
Would be great to refactor this all into a set of small common helpers.
221+
222+
Contact: Daniel Vetter
223+
224+
Put a reservation_object into drm_gem_object
225+
--------------------------------------------
226+
227+
This would remove the need for the ->gem_prime_res_obj callback. It would also
228+
allow us to implement generic helpers for waiting for a bo, allowing for quite a
229+
bit of refactoring in the various wait ioctl implementations.
230+
231+
Contact: Daniel Vetter
232+
215233
idr_init_base()
216234
---------------
217235

‎Documentation/gpu/xen-front.rst

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1+
====================================================
2+
drm/xen-front Xen para-virtualized frontend driver
3+
====================================================
4+
5+
This frontend driver implements Xen para-virtualized display
6+
according to the display protocol described at
7+
include/xen/interface/io/displif.h
8+
9+
Driver modes of operation in terms of display buffers used
10+
==========================================================
11+
12+
.. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
13+
:doc: Driver modes of operation in terms of display buffers used
14+
15+
Buffers allocated by the frontend driver
16+
----------------------------------------
17+
18+
.. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
19+
:doc: Buffers allocated by the frontend driver
20+
21+
Buffers allocated by the backend
22+
--------------------------------
23+
24+
.. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
25+
:doc: Buffers allocated by the backend
26+
27+
Driver limitations
28+
==================
29+
30+
.. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
31+
:doc: Driver limitations

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