Skip to content

Commit 162b20d

Browse files
airliedairlied
committed
Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more patches for 4.8. Mostly bug fixes and some prep work for iceland powerplay support. I have a couple polaris patches and Edward's misc cleanups that require a merge with Linus'. I don't know if you are planning a merge anytime soon. [airlied: fixed up endian vs 32-bit change in ppatomctrl] * 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (26 commits) drm/amdgpu: comment out unused defaults_bonaire_pro static const structures to fix the build drm/amdgpu: temporary comment out unused static const structures to fix the build drm/amdgpu: S3 resume fail on Polaris10 drm/amd/powerplay: add pp_tables_get_response_times function in process pptables drm/amd/powerplay: fix the incorrect return value drm/amd/powerplay: add atomctrl_get_voltage_evv function in ppatomctrl drm/amdgpu: add new definitions into ppsmc.h for iceland drm/amd/powerplay: add SMU register macro for future use drm/amdgpu: add ucode_start_address into cgs_firmware_info drm/amdgpu: no need load microcode at sdma if powerplay is enabled drm/amdgpu: rename smumgr to smum for dpm drm/amdgpu: disable GFX PG on CZ/BR/ST drivers: gpu: drm: amd: powerplay: hwmgr: Remove unused variable drm/amdgpu: return -ENOSPC when running out of UVD handles drm/amdgpu: trace need_flush in grab_vm as well drm/amdgpu: always signal all fences drm/amdgpu: check flush fence context instead of same ring v2 drm/radeon: support backlight control for UNIPHY3 drm/amdgpu: support backlight control for UNIPHY3 drm/amdgpu: remove usec timeout loop from IB tests ...
2 parents c3f8d86 + 5ef8292 commit 162b20d

30 files changed

+469
-360
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -752,6 +752,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
752752

753753
if (!adev->pm.fw) {
754754
switch (adev->asic_type) {
755+
case CHIP_TOPAZ:
756+
strcpy(fw_name, "amdgpu/topaz_smc.bin");
757+
break;
755758
case CHIP_TONGA:
756759
strcpy(fw_name, "amdgpu/tonga_smc.bin");
757760
break;
@@ -800,6 +803,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
800803

801804
info->version = adev->pm.fw_version;
802805
info->image_size = ucode_size;
806+
info->ucode_start_address = ucode_start_address;
803807
info->kptr = (void *)src;
804808
}
805809
return 0;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -204,16 +204,25 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
204204
if (seq != ring->fence_drv.sync_seq)
205205
amdgpu_fence_schedule_fallback(ring);
206206

207-
while (last_seq != seq) {
207+
if (unlikely(seq == last_seq))
208+
return;
209+
210+
last_seq &= drv->num_fences_mask;
211+
seq &= drv->num_fences_mask;
212+
213+
do {
208214
struct fence *fence, **ptr;
209215

210-
ptr = &drv->fences[++last_seq & drv->num_fences_mask];
216+
++last_seq;
217+
last_seq &= drv->num_fences_mask;
218+
ptr = &drv->fences[last_seq];
211219

212220
/* There is always exactly one thread signaling this fence slot */
213221
fence = rcu_dereference_protected(*ptr, 1);
214222
RCU_INIT_POINTER(*ptr, NULL);
215223

216-
BUG_ON(!fence);
224+
if (!fence)
225+
continue;
217226

218227
r = fence_signal(fence);
219228
if (!r)
@@ -222,7 +231,7 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
222231
BUG();
223232

224233
fence_put(fence);
225-
}
234+
} while (last_seq != seq);
226235
}
227236

228237
/**

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
122122
bool skip_preamble, need_ctx_switch;
123123
unsigned patch_offset = ~0;
124124
struct amdgpu_vm *vm;
125-
struct fence *hwf;
126125
uint64_t ctx;
127126

128127
unsigned i;
@@ -190,7 +189,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
190189
if (ring->funcs->emit_hdp_invalidate)
191190
amdgpu_ring_emit_hdp_invalidate(ring);
192191

193-
r = amdgpu_fence_emit(ring, &hwf);
192+
r = amdgpu_fence_emit(ring, f);
194193
if (r) {
195194
dev_err(adev->dev, "failed to emit fence (%d)\n", r);
196195
if (job && job->vm_id)
@@ -205,9 +204,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
205204
AMDGPU_FENCE_FLAG_64BIT);
206205
}
207206

208-
if (f)
209-
*f = fence_get(hwf);
210-
211207
if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
212208
amdgpu_ring_patch_cond_exec(ring, patch_offset);
213209

‎drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -172,15 +172,13 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
172172
trace_amdgpu_sched_run_job(job);
173173
r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
174174
job->sync.last_vm_update, job, &fence);
175-
if (r) {
175+
if (r)
176176
DRM_ERROR("Error scheduling IBs (%d)\n", r);
177-
goto err;
178-
}
179177

180-
err:
181178
/* if gpu reset, hw fence will be replaced here */
182179
fence_put(job->fence);
183-
job->fence = fence;
180+
job->fence = fence_get(fence);
181+
amdgpu_job_free_resources(job);
184182
return fence;
185183
}
186184

‎drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -149,24 +149,26 @@ TRACE_EVENT(amdgpu_sched_run_job,
149149

150150

151151
TRACE_EVENT(amdgpu_vm_grab_id,
152-
TP_PROTO(struct amdgpu_vm *vm, int ring, unsigned vmid,
153-
uint64_t pd_addr),
154-
TP_ARGS(vm, ring, vmid, pd_addr),
152+
TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),
153+
TP_ARGS(vm, ring, job),
155154
TP_STRUCT__entry(
156155
__field(struct amdgpu_vm *, vm)
157156
__field(u32, ring)
158157
__field(u32, vmid)
159158
__field(u64, pd_addr)
159+
__field(u32, needs_flush)
160160
),
161161

162162
TP_fast_assign(
163163
__entry->vm = vm;
164164
__entry->ring = ring;
165-
__entry->vmid = vmid;
166-
__entry->pd_addr = pd_addr;
165+
__entry->vmid = job->vm_id;
166+
__entry->pd_addr = job->vm_pd_addr;
167+
__entry->needs_flush = job->vm_needs_flush;
167168
),
168-
TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx", __entry->vm,
169-
__entry->ring, __entry->vmid, __entry->pd_addr)
169+
TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx needs_flush=%u",
170+
__entry->vm, __entry->ring, __entry->vmid,
171+
__entry->pd_addr, __entry->needs_flush)
170172
);
171173

172174
TRACE_EVENT(amdgpu_vm_bo_map,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
4040
#include "uvd/uvd_4_2_d.h"
4141

4242
/* 1 second timeout */
43-
#define UVD_IDLE_TIMEOUT_MS 1000
43+
#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
4444
/* Polaris10/11 firmware version */
4545
#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
4646

@@ -662,7 +662,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
662662
}
663663

664664
DRM_ERROR("No more free UVD handles!\n");
665-
return -EINVAL;
665+
return -ENOSPC;
666666

667667
case 1:
668668
/* it's a decode msg, calc buffer sizes */
@@ -968,7 +968,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
968968

969969
if (direct) {
970970
r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
971-
job->fence = f;
971+
job->fence = fence_get(f);
972972
if (r)
973973
goto err_free;
974974

@@ -1114,16 +1114,15 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
11141114
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
11151115
}
11161116
} else {
1117-
schedule_delayed_work(&adev->uvd.idle_work,
1118-
msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1117+
schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
11191118
}
11201119
}
11211120

11221121
static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
11231122
{
11241123
bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
11251124
set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1126-
msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1125+
UVD_IDLE_TIMEOUT);
11271126

11281127
if (set_clocks) {
11291128
if (adev->pm.dpm_enabled) {

0 commit comments

Comments
 (0)