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2574 | 2574 | #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
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2575 | 2575 | #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
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2576 | 2576 | #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
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2577 |
| -#define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ |
2578 |
| -#define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ |
| 2577 | +/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| 2578 | + * capability only. |
| 2579 | + */ |
| 2580 | +#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c |
| 2581 | +/* enum: PM discard_bb_overflow counter. Valid for EF10 with |
| 2582 | + * PM_AND_RXDP_COUNTERS capability only. |
| 2583 | + */ |
| 2584 | +#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d |
| 2585 | +/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| 2586 | + * capability only. |
| 2587 | + */ |
| 2588 | +#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e |
| 2589 | +/* enum: PM discard_vfifo_full counter. Valid for EF10 with |
| 2590 | + * PM_AND_RXDP_COUNTERS capability only. |
| 2591 | + */ |
| 2592 | +#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f |
| 2593 | +/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| 2594 | + * capability only. |
| 2595 | + */ |
| 2596 | +#define MC_CMD_MAC_PM_TRUNC_QBB 0x40 |
| 2597 | +/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| 2598 | + * capability only. |
| 2599 | + */ |
| 2600 | +#define MC_CMD_MAC_PM_DISCARD_QBB 0x41 |
| 2601 | +/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| 2602 | + * capability only. |
| 2603 | + */ |
| 2604 | +#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 |
| 2605 | +/* enum: RXDP counter: Number of packets dropped due to the queue being |
| 2606 | + * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| 2607 | + */ |
| 2608 | +#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 |
| 2609 | +/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 |
| 2610 | + * with PM_AND_RXDP_COUNTERS capability only. |
| 2611 | + */ |
| 2612 | +#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 |
| 2613 | +/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with |
| 2614 | + * PM_AND_RXDP_COUNTERS capability only. |
| 2615 | + */ |
| 2616 | +#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 |
| 2617 | +/* enum: RXDP counter: Number of times an emergency descriptor fetch was |
| 2618 | + * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| 2619 | + */ |
| 2620 | +#define MC_CMD_MAC_RXDP_EMERGENCY_FETCH_CONDITIONS 0x47 |
| 2621 | +/* enum: RXDP counter: Number of times the DPCPU waited for an existing |
| 2622 | + * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| 2623 | + */ |
| 2624 | +#define MC_CMD_MAC_RXDP_EMERGENCY_WAIT_CONDITIONS 0x48 |
| 2625 | +/* enum: Start of GMAC stats buffer space, for Siena only. */ |
| 2626 | +#define MC_CMD_GMAC_DMABUF_START 0x40 |
| 2627 | +/* enum: End of GMAC stats buffer space, for Siena only. */ |
| 2628 | +#define MC_CMD_GMAC_DMABUF_END 0x5f |
2579 | 2629 | #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
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2580 | 2630 | #define MC_CMD_MAC_NSTATS 0x61 /* enum */
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2581 | 2631 |
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5065 | 5115 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
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5066 | 5116 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
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5067 | 5117 | #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
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| 5118 | +#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 |
| 5119 | +#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 |
5068 | 5120 | /* RxDPCPU firmware id. */
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5069 | 5121 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
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5070 | 5122 | #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
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