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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann: "As usual, the drivers/tee and drivers/reset subsystems get merged here, with the expected set of smaller updates and some new hardware support. The tee subsystem now supports device drivers to be attached to a tee, the first example here is a random number driver with its implementation in the secure world. Three new power domain drivers get added for specific chip families: - Broadcom BCM283x chips (used in Raspberry Pi) - Qualcomm Snapdragon phone chips - Xilinx ZynqMP FPGA SoCs One new driver is added to talk to the BPMP firmware on NVIDIA Tegra210 Existing drivers are extended for new SoC variants from NXP, NVIDIA, Amlogic and Qualcomm" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (113 commits) tee: optee: update optee_msg.h and optee_smc.h to dual license tee: add cancellation support to client interface dpaa2-eth: configure the cache stashing amount on a queue soc: fsl: dpio: configure cache stashing destination soc: fsl: dpio: enable frame data cache stashing per software portal soc: fsl: guts: make fsl_guts_get_svr() static hwrng: make symbol 'optee_rng_id_table' static tee: optee: Fix unsigned comparison with less than zero hwrng: Fix unsigned comparison with less than zero tee: fix possible error pointer ctx dereferencing hwrng: optee: Initialize some structs using memset instead of braces tee: optee: Initialize some structs using memset instead of braces soc: fsl: dpio: fix memory leak of a struct qbman on error exit path clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static soc: qcom: llcc-slice: Fix typos qcom: soc: llcc-slice: Consolidate some code qcom: soc: llcc-slice: Clear the global drv_data pointer on error drivers: soc: xilinx: Add ZynqMP power domain driver firmware: xilinx: Add APIs to control node status/power dt-bindings: power: Add ZynqMP power domain bindings ...
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‎Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
5858
domain binding[2].
5959

6060
Required properties:
61-
- compatible: Should be "fsl,imx8qxp-scu-pd".
61+
- compatible: Should be one of:
62+
"fsl,imx8qm-scu-pd",
63+
"fsl,imx8qxp-scu-pd"
64+
followed by "fsl,scu-pd"
65+
6266
- #power-domain-cells: Must be 1. Contains the Resource ID used by
6367
SCU commands.
6468
See detailed Resource ID list from:
@@ -157,7 +161,7 @@ firmware {
157161
};
158162

159163
pd: imx8qx-pd {
160-
compatible = "fsl,imx8qxp-scu-pd";
164+
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
161165
#power-domain-cells = <1>;
162166
};
163167

‎Documentation/devicetree/bindings/bus/imx-weim.txt

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@ Optional properties:
4747
Timing property for child nodes. It is mandatory, not optional.
4848

4949
- fsl,weim-cs-timing: The timing array, contains timing values for the
50-
child node. We can get the CS index from the child
51-
node's "reg" property. The number of registers depends
52-
on the selected chip.
50+
child node. We get the CS indexes from the address
51+
ranges in the child node's "reg" property.
52+
The number of registers depends on the selected chip:
5353
For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
5454
registers: CSxU, CSxL.
5555
For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
@@ -80,3 +80,29 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
8080
0x0000c000 0x1404a38e 0x00000000>;
8181
};
8282
};
83+
84+
Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
85+
86+
In this case, both chip select 0 and 1 will be configured with the same timing
87+
array values.
88+
89+
weim: weim@21b8000 {
90+
compatible = "fsl,imx6q-weim";
91+
reg = <0x021b8000 0x4000>;
92+
clocks = <&clks 196>;
93+
#address-cells = <2>;
94+
#size-cells = <1>;
95+
ranges = <0 0 0x08000000 0x02000000
96+
1 0 0x0a000000 0x02000000
97+
2 0 0x0c000000 0x02000000
98+
3 0 0x0e000000 0x02000000>;
99+
fsl,weim-cs-gpr = <&gpr>;
100+
101+
acme@0 {
102+
compatible = "acme,whatever";
103+
reg = <0 0 0x100>, <0 0x400000 0x800>,
104+
<1 0x400000 0x800>;
105+
fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
106+
0x00000000 0xa0000240 0x00000000>;
107+
};
108+
};

‎Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt

Lines changed: 46 additions & 0 deletions
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@@ -0,0 +1,46 @@
1+
--------------------------------------------------------------------------
2+
= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3+
--------------------------------------------------------------------------
4+
The nvmem_firmware node provides access to the hardware related data
5+
like soc revision, IDCODE... etc, By using the firmware interface.
6+
7+
Required properties:
8+
- compatible: should be "xlnx,zynqmp-nvmem-fw"
9+
10+
= Data cells =
11+
Are child nodes of silicon id, bindings of which as described in
12+
bindings/nvmem/nvmem.txt
13+
14+
-------
15+
Example
16+
-------
17+
firmware {
18+
zynqmp_firmware: zynqmp-firmware {
19+
compatible = "xlnx,zynqmp-firmware";
20+
method = "smc";
21+
22+
nvmem_firmware {
23+
compatible = "xlnx,zynqmp-nvmem-fw";
24+
#address-cells = <1>;
25+
#size-cells = <1>;
26+
27+
/* Data cells */
28+
soc_revision: soc_revision {
29+
reg = <0x0 0x4>;
30+
};
31+
};
32+
};
33+
};
34+
35+
= Data consumers =
36+
Are device nodes which consume nvmem data cells.
37+
38+
For example:
39+
pcap {
40+
...
41+
42+
nvmem-cells = <&soc_revision>;
43+
nvmem-cell-names = "soc_revision";
44+
45+
...
46+
};

‎Documentation/devicetree/bindings/opp/opp.txt

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Original file line numberDiff line numberDiff line change
@@ -129,6 +129,9 @@ Optional properties:
129129
- opp-microamp-<name>: Named opp-microamp property. Similar to
130130
opp-microvolt-<name> property, but for microamp instead.
131131

132+
- opp-level: A value representing the performance level of the device,
133+
expressed as a 32-bit integer.
134+
132135
- clock-latency-ns: Specifies the maximum possible transition latency (in
133136
nanoseconds) for switching to this OPP from any other OPP.
134137

‎Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt

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Original file line numberDiff line numberDiff line change
@@ -32,6 +32,9 @@ Required properties:
3232
Optional properties:
3333

3434
- power-supply: Power supply used to power the domain
35+
- clocks: a number of phandles to clocks that need to be enabled during
36+
domain power-up sequencing to ensure reset propagation into devices
37+
located inside this power domain
3538

3639
Example:
3740

‎Documentation/devicetree/bindings/power/qcom,rpmpd.txt

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@@ -0,0 +1,145 @@
1+
Qualcomm RPM/RPMh Power domains
2+
3+
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
4+
which then translates it into a corresponding voltage on a rail
5+
6+
Required Properties:
7+
- compatible: Should be one of the following
8+
* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
9+
* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
10+
- #power-domain-cells: number of cells in Power domain specifier
11+
must be 1.
12+
- operating-points-v2: Phandle to the OPP table for the Power domain.
13+
Refer to Documentation/devicetree/bindings/power/power_domain.txt
14+
and Documentation/devicetree/bindings/opp/opp.txt for more details
15+
16+
Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for
17+
various OPPs for different platforms as well as Power domain indexes
18+
19+
Example: rpmh power domain controller and OPP table
20+
21+
#include <dt-bindings/power/qcom-rpmhpd.h>
22+
23+
opp-level values specified in the OPP tables for RPMh power domains
24+
should use the RPMH_REGULATOR_LEVEL_* constants from
25+
<dt-bindings/power/qcom-rpmhpd.h>
26+
27+
rpmhpd: power-controller {
28+
compatible = "qcom,sdm845-rpmhpd";
29+
#power-domain-cells = <1>;
30+
operating-points-v2 = <&rpmhpd_opp_table>;
31+
32+
rpmhpd_opp_table: opp-table {
33+
compatible = "operating-points-v2";
34+
35+
rpmhpd_opp_ret: opp1 {
36+
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
37+
};
38+
39+
rpmhpd_opp_min_svs: opp2 {
40+
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
41+
};
42+
43+
rpmhpd_opp_low_svs: opp3 {
44+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
45+
};
46+
47+
rpmhpd_opp_svs: opp4 {
48+
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
49+
};
50+
51+
rpmhpd_opp_svs_l1: opp5 {
52+
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
53+
};
54+
55+
rpmhpd_opp_nom: opp6 {
56+
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
57+
};
58+
59+
rpmhpd_opp_nom_l1: opp7 {
60+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
61+
};
62+
63+
rpmhpd_opp_nom_l2: opp8 {
64+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
65+
};
66+
67+
rpmhpd_opp_turbo: opp9 {
68+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
69+
};
70+
71+
rpmhpd_opp_turbo_l1: opp10 {
72+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
73+
};
74+
};
75+
};
76+
77+
Example: rpm power domain controller and OPP table
78+
79+
rpmpd: power-controller {
80+
compatible = "qcom,msm8996-rpmpd";
81+
#power-domain-cells = <1>;
82+
operating-points-v2 = <&rpmpd_opp_table>;
83+
84+
rpmpd_opp_table: opp-table {
85+
compatible = "operating-points-v2";
86+
87+
rpmpd_opp_low: opp1 {
88+
opp-level = <1>;
89+
};
90+
91+
rpmpd_opp_ret: opp2 {
92+
opp-level = <2>;
93+
};
94+
95+
rpmpd_opp_svs: opp3 {
96+
opp-level = <3>;
97+
};
98+
99+
rpmpd_opp_normal: opp4 {
100+
opp-level = <4>;
101+
};
102+
103+
rpmpd_opp_high: opp5 {
104+
opp-level = <5>;
105+
};
106+
107+
rpmpd_opp_turbo: opp6 {
108+
opp-level = <6>;
109+
};
110+
};
111+
};
112+
113+
Example: Client/Consumer device using OPP table
114+
115+
leaky-device0@12350000 {
116+
compatible = "foo,i-leak-current";
117+
reg = <0x12350000 0x1000>;
118+
power-domains = <&rpmhpd SDM845_MX>;
119+
operating-points-v2 = <&leaky_opp_table>;
120+
};
121+
122+
123+
leaky_opp_table: opp-table {
124+
compatible = "operating-points-v2";
125+
126+
opp1 {
127+
opp-hz = /bits/ 64 <144000>;
128+
required-opps = <&rpmhpd_opp_low>;
129+
};
130+
131+
opp2 {
132+
opp-hz = /bits/ 64 <400000>;
133+
required-opps = <&rpmhpd_opp_ret>;
134+
};
135+
136+
opp3 {
137+
opp-hz = /bits/ 64 <20000000>;
138+
required-opps = <&rpmpd_opp_svs>;
139+
};
140+
141+
opp4 {
142+
opp-hz = /bits/ 64 <25000000>;
143+
required-opps = <&rpmpd_opp_normal>;
144+
};
145+
};

‎Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt

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1+
--------------------------------------------------------------------
2+
Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
3+
--------------------------------------------------------------------
4+
The zynqmp-power node describes the power management configurations.
5+
It will control remote suspend/shutdown interfaces.
6+
7+
Required properties:
8+
- compatible: Must contain: "xlnx,zynqmp-power"
9+
- interrupts: Interrupt specifier
10+
11+
-------
12+
Example
13+
-------
14+
15+
firmware {
16+
zynqmp_firmware: zynqmp-firmware {
17+
compatible = "xlnx,zynqmp-firmware";
18+
method = "smc";
19+
20+
zynqmp_power: zynqmp-power {
21+
compatible = "xlnx,zynqmp-power";
22+
interrupts = <0 35 4>;
23+
};
24+
};
25+
};

‎Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt

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1+
-----------------------------------------------------------
2+
Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
3+
-----------------------------------------------------------
4+
The binding for zynqmp-power-controller follow the common
5+
generic PM domain binding[1].
6+
7+
[1] Documentation/devicetree/bindings/power/power_domain.txt
8+
9+
== Zynq MPSoC Generic PM Domain Node ==
10+
11+
Required property:
12+
- Below property should be in zynqmp-firmware node.
13+
- #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
14+
15+
Power domain ID indexes are mentioned in
16+
include/dt-bindings/power/xlnx-zynqmp-power.h.
17+
18+
-------
19+
Example
20+
-------
21+
22+
firmware {
23+
zynqmp_firmware: zynqmp-firmware {
24+
...
25+
#power-domain-cells = <1>;
26+
...
27+
};
28+
};
29+
30+
sata {
31+
...
32+
power-domains = <&zynqmp_firmware 28>;
33+
...
34+
};

‎Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt

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@@ -0,0 +1,27 @@
1+
Broadcom STB SW_INIT-style reset controller
2+
===========================================
3+
4+
Broadcom STB SoCs have a SW_INIT-style reset controller with separate
5+
SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
6+
reset lines.
7+
8+
Please also refer to reset.txt in this directory for common reset
9+
controller binding usage.
10+
11+
Required properties:
12+
- compatible: should be brcm,brcmstb-reset
13+
- reg: register base and length
14+
- #reset-cells: must be set to 1
15+
16+
Example:
17+
18+
reset: reset-controller@8404318 {
19+
compatible = "brcm,brcmstb-reset";
20+
reg = <0x8404318 0x30>;
21+
#reset-cells = <1>;
22+
};
23+
24+
&ethernet_switch {
25+
resets = <&reset>;
26+
reset-names = "switch";
27+
};

‎Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset
55
controller binding usage.
66

77
Required properties:
8-
- compatible: Should be "fsl,imx7d-src", "syscon"
8+
- compatible:
9+
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
10+
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
911
- reg: should be register base and length as documented in the
1012
datasheet
1113
- interrupts: Should contain SRC interrupt
@@ -44,4 +46,5 @@ Example:
4446

4547

4648
For list of all valid reset indicies see
47-
<dt-bindings/reset/imx7-reset.h>
49+
<dt-bindings/reset/imx7-reset.h> for i.MX7 and
50+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ

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