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Fabrizio Castrohorms
Fabrizio Castro
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horms
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arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports, incl. clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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‎arch/arm64/boot/dts/renesas/r8a774a1.dtsi

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,94 @@
144144
#power-domain-cells = <1>;
145145
};
146146

147+
hscif0: serial@e6540000 {
148+
compatible = "renesas,hscif-r8a774a1",
149+
"renesas,rcar-gen3-hscif",
150+
"renesas,hscif";
151+
reg = <0 0xe6540000 0 0x60>;
152+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
153+
clocks = <&cpg CPG_MOD 520>,
154+
<&cpg CPG_CORE 19>,
155+
<&scif_clk>;
156+
clock-names = "fck", "brg_int", "scif_clk";
157+
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
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<&dmac2 0x31>, <&dmac2 0x30>;
159+
dma-names = "tx", "rx", "tx", "rx";
160+
power-domains = <&sysc 32>;
161+
resets = <&cpg 520>;
162+
status = "disabled";
163+
};
164+
165+
hscif1: serial@e6550000 {
166+
compatible = "renesas,hscif-r8a774a1",
167+
"renesas,rcar-gen3-hscif",
168+
"renesas,hscif";
169+
reg = <0 0xe6550000 0 0x60>;
170+
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
171+
clocks = <&cpg CPG_MOD 519>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
174+
clock-names = "fck", "brg_int", "scif_clk";
175+
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
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<&dmac2 0x33>, <&dmac2 0x32>;
177+
dma-names = "tx", "rx", "tx", "rx";
178+
power-domains = <&sysc 32>;
179+
resets = <&cpg 519>;
180+
status = "disabled";
181+
};
182+
183+
hscif2: serial@e6560000 {
184+
compatible = "renesas,hscif-r8a774a1",
185+
"renesas,rcar-gen3-hscif",
186+
"renesas,hscif";
187+
reg = <0 0xe6560000 0 0x60>;
188+
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
189+
clocks = <&cpg CPG_MOD 518>,
190+
<&cpg CPG_CORE 19>,
191+
<&scif_clk>;
192+
clock-names = "fck", "brg_int", "scif_clk";
193+
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
194+
<&dmac2 0x35>, <&dmac2 0x34>;
195+
dma-names = "tx", "rx", "tx", "rx";
196+
power-domains = <&sysc 32>;
197+
resets = <&cpg 518>;
198+
status = "disabled";
199+
};
200+
201+
hscif3: serial@e66a0000 {
202+
compatible = "renesas,hscif-r8a774a1",
203+
"renesas,rcar-gen3-hscif",
204+
"renesas,hscif";
205+
reg = <0 0xe66a0000 0 0x60>;
206+
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
207+
clocks = <&cpg CPG_MOD 517>,
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<&cpg CPG_CORE 19>,
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<&scif_clk>;
210+
clock-names = "fck", "brg_int", "scif_clk";
211+
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
212+
dma-names = "tx", "rx";
213+
power-domains = <&sysc 32>;
214+
resets = <&cpg 517>;
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status = "disabled";
216+
};
217+
218+
hscif4: serial@e66b0000 {
219+
compatible = "renesas,hscif-r8a774a1",
220+
"renesas,rcar-gen3-hscif",
221+
"renesas,hscif";
222+
reg = <0 0xe66b0000 0 0x60>;
223+
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
224+
clocks = <&cpg CPG_MOD 516>,
225+
<&cpg CPG_CORE 19>,
226+
<&scif_clk>;
227+
clock-names = "fck", "brg_int", "scif_clk";
228+
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
229+
dma-names = "tx", "rx";
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power-domains = <&sysc 32>;
231+
resets = <&cpg 516>;
232+
status = "disabled";
233+
};
234+
147235
dmac0: dma-controller@e6700000 {
148236
compatible = "renesas,dmac-r8a774a1",
149237
"renesas,rcar-dmac";
@@ -246,6 +334,103 @@
246334
dma-channels = <16>;
247335
};
248336

337+
scif0: serial@e6e60000 {
338+
compatible = "renesas,scif-r8a774a1",
339+
"renesas,rcar-gen3-scif", "renesas,scif";
340+
reg = <0 0xe6e60000 0 0x40>;
341+
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
342+
clocks = <&cpg CPG_MOD 207>,
343+
<&cpg CPG_CORE 19>,
344+
<&scif_clk>;
345+
clock-names = "fck", "brg_int", "scif_clk";
346+
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
347+
<&dmac2 0x51>, <&dmac2 0x50>;
348+
dma-names = "tx", "rx", "tx", "rx";
349+
power-domains = <&sysc 32>;
350+
resets = <&cpg 207>;
351+
status = "disabled";
352+
};
353+
354+
scif1: serial@e6e68000 {
355+
compatible = "renesas,scif-r8a774a1",
356+
"renesas,rcar-gen3-scif", "renesas,scif";
357+
reg = <0 0xe6e68000 0 0x40>;
358+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
359+
clocks = <&cpg CPG_MOD 206>,
360+
<&cpg CPG_CORE 19>,
361+
<&scif_clk>;
362+
clock-names = "fck", "brg_int", "scif_clk";
363+
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
364+
<&dmac2 0x53>, <&dmac2 0x52>;
365+
dma-names = "tx", "rx", "tx", "rx";
366+
power-domains = <&sysc 32>;
367+
resets = <&cpg 206>;
368+
status = "disabled";
369+
};
370+
371+
scif2: serial@e6e88000 {
372+
compatible = "renesas,scif-r8a774a1",
373+
"renesas,rcar-gen3-scif", "renesas,scif";
374+
reg = <0 0xe6e88000 0 0x40>;
375+
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
376+
clocks = <&cpg CPG_MOD 310>,
377+
<&cpg CPG_CORE 19>,
378+
<&scif_clk>;
379+
clock-names = "fck", "brg_int", "scif_clk";
380+
power-domains = <&sysc 32>;
381+
resets = <&cpg 310>;
382+
status = "disabled";
383+
};
384+
385+
scif3: serial@e6c50000 {
386+
compatible = "renesas,scif-r8a774a1",
387+
"renesas,rcar-gen3-scif", "renesas,scif";
388+
reg = <0 0xe6c50000 0 0x40>;
389+
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
390+
clocks = <&cpg CPG_MOD 204>,
391+
<&cpg CPG_CORE 19>,
392+
<&scif_clk>;
393+
clock-names = "fck", "brg_int", "scif_clk";
394+
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
395+
dma-names = "tx", "rx";
396+
power-domains = <&sysc 32>;
397+
resets = <&cpg 204>;
398+
status = "disabled";
399+
};
400+
401+
scif4: serial@e6c40000 {
402+
compatible = "renesas,scif-r8a774a1",
403+
"renesas,rcar-gen3-scif", "renesas,scif";
404+
reg = <0 0xe6c40000 0 0x40>;
405+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
406+
clocks = <&cpg CPG_MOD 203>,
407+
<&cpg CPG_CORE 19>,
408+
<&scif_clk>;
409+
clock-names = "fck", "brg_int", "scif_clk";
410+
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
411+
dma-names = "tx", "rx";
412+
power-domains = <&sysc 32>;
413+
resets = <&cpg 203>;
414+
status = "disabled";
415+
};
416+
417+
scif5: serial@e6f30000 {
418+
compatible = "renesas,scif-r8a774a1",
419+
"renesas,rcar-gen3-scif", "renesas,scif";
420+
reg = <0 0xe6f30000 0 0x40>;
421+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
422+
clocks = <&cpg CPG_MOD 202>,
423+
<&cpg CPG_CORE 19>,
424+
<&scif_clk>;
425+
clock-names = "fck", "brg_int", "scif_clk";
426+
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
427+
<&dmac2 0x5b>, <&dmac2 0x5a>;
428+
dma-names = "tx", "rx", "tx", "rx";
429+
power-domains = <&sysc 32>;
430+
resets = <&cpg 202>;
431+
status = "disabled";
432+
};
433+
249434
gic: interrupt-controller@f1010000 {
250435
compatible = "arm,gic-400";
251436
#interrupt-cells = <3>;

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