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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto update from Herbert Xu: "Here is the crypto update for 4.2: API: - Convert RNG interface to new style. - New AEAD interface with one SG list for AD and plain/cipher text. All external AEAD users have been converted. - New asymmetric key interface (akcipher). Algorithms: - Chacha20, Poly1305 and RFC7539 support. - New RSA implementation. - Jitter RNG. - DRBG is now seeded with both /dev/random and Jitter RNG. If kernel pool isn't ready then DRBG will be reseeded when it is. - DRBG is now the default crypto API RNG, replacing krng. - 842 compression (previously part of powerpc nx driver). Drivers: - Accelerated SHA-512 for arm64. - New Marvell CESA driver that supports DMA and more algorithms. - Updated powerpc nx 842 support. - Added support for SEC1 hardware to talitos" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (292 commits) crypto: marvell/cesa - remove COMPILE_TEST dependency crypto: algif_aead - Temporarily disable all AEAD algorithms crypto: af_alg - Forbid the use internal algorithms crypto: echainiv - Only hold RNG during initialisation crypto: seqiv - Add compatibility support without RNG crypto: eseqiv - Offer normal cipher functionality without RNG crypto: chainiv - Offer normal cipher functionality without RNG crypto: user - Add CRYPTO_MSG_DELRNG crypto: user - Move cryptouser.h to uapi crypto: rng - Do not free default RNG when it becomes unused crypto: skcipher - Allow givencrypt to be NULL crypto: sahara - propagate the error on clk_disable_unprepare() failure crypto: rsa - fix invalid select for AKCIPHER crypto: picoxcell - Update to the current clk API crypto: nx - Check for bogus firmware properties crypto: marvell/cesa - add DT bindings documentation crypto: marvell/cesa - add support for Kirkwood and Dove SoCs crypto: marvell/cesa - add support for Orion SoCs crypto: marvell/cesa - add allhwsupport module parameter crypto: marvell/cesa - add support for all armada SoCs ...
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‎Documentation/DocBook/crypto-API.tmpl

Lines changed: 39 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@
119119

120120
<para>
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Note: The terms "transformation" and cipher algorithm are used
122-
interchangably.
122+
interchangeably.
123123
</para>
124124
</sect1>
125125

@@ -536,8 +536,8 @@
536536

537537
<para>
538538
For other use cases of AEAD ciphers, the ASCII art applies as
539-
well, but the caller may not use the GIVCIPHER interface. In
540-
this case, the caller must generate the IV.
539+
well, but the caller may not use the AEAD cipher with a separate
540+
IV generator. In this case, the caller must generate the IV.
541541
</para>
542542

543543
<para>
@@ -584,8 +584,8 @@ kernel crypto API | IPSEC Layer
584584
|
585585
+-----------+ |
586586
| | (1)
587-
| givcipher | <----------------------------------- esp_output
588-
| (seqiv) | ---+
587+
| aead | <----------------------------------- esp_output
588+
| (seqniv) | ---+
589589
+-----------+ |
590590
| (2)
591591
+-----------+ |
@@ -620,8 +620,8 @@ kernel crypto API | IPSEC Layer
620620
<orderedlist>
621621
<listitem>
622622
<para>
623-
esp_output() invokes crypto_aead_givencrypt() to trigger an encryption
624-
operation of the GIVCIPHER implementation.
623+
esp_output() invokes crypto_aead_encrypt() to trigger an encryption
624+
operation of the AEAD cipher with IV generator.
625625
</para>
626626

627627
<para>
@@ -1563,7 +1563,7 @@ struct sockaddr_alg sa = {
15631563

15641564
<sect1><title>Zero-Copy Interface</title>
15651565
<para>
1566-
In addition to the send/write/read/recv system call familty, the AF_ALG
1566+
In addition to the send/write/read/recv system call family, the AF_ALG
15671567
interface can be accessed with the zero-copy interface of splice/vmsplice.
15681568
As the name indicates, the kernel tries to avoid a copy operation into
15691569
kernel space.
@@ -1669,9 +1669,19 @@ read(opfd, out, outlen);
16691669
</chapter>
16701670

16711671
<chapter id="API"><title>Programming Interface</title>
1672+
<para>
1673+
Please note that the kernel crypto API contains the AEAD givcrypt
1674+
API (crypto_aead_giv* and aead_givcrypt_* function calls in
1675+
include/crypto/aead.h). This API is obsolete and will be removed
1676+
in the future. To obtain the functionality of an AEAD cipher with
1677+
internal IV generation, use the IV generator as a regular cipher.
1678+
For example, rfc4106(gcm(aes)) is the AEAD cipher with external
1679+
IV generation and seqniv(rfc4106(gcm(aes))) implies that the kernel
1680+
crypto API generates the IV. Different IV generators are available.
1681+
</para>
16721682
<sect1><title>Block Cipher Context Data Structures</title>
16731683
!Pinclude/linux/crypto.h Block Cipher Context Data Structures
1674-
!Finclude/linux/crypto.h aead_request
1684+
!Finclude/crypto/aead.h aead_request
16751685
</sect1>
16761686
<sect1><title>Block Cipher Algorithm Definitions</title>
16771687
!Pinclude/linux/crypto.h Block Cipher Algorithm Definitions
@@ -1680,7 +1690,7 @@ read(opfd, out, outlen);
16801690
!Finclude/linux/crypto.h aead_alg
16811691
!Finclude/linux/crypto.h blkcipher_alg
16821692
!Finclude/linux/crypto.h cipher_alg
1683-
!Finclude/linux/crypto.h rng_alg
1693+
!Finclude/crypto/rng.h rng_alg
16841694
</sect1>
16851695
<sect1><title>Asynchronous Block Cipher API</title>
16861696
!Pinclude/linux/crypto.h Asynchronous Block Cipher API
@@ -1704,26 +1714,27 @@ read(opfd, out, outlen);
17041714
!Finclude/linux/crypto.h ablkcipher_request_set_crypt
17051715
</sect1>
17061716
<sect1><title>Authenticated Encryption With Associated Data (AEAD) Cipher API</title>
1707-
!Pinclude/linux/crypto.h Authenticated Encryption With Associated Data (AEAD) Cipher API
1708-
!Finclude/linux/crypto.h crypto_alloc_aead
1709-
!Finclude/linux/crypto.h crypto_free_aead
1710-
!Finclude/linux/crypto.h crypto_aead_ivsize
1711-
!Finclude/linux/crypto.h crypto_aead_authsize
1712-
!Finclude/linux/crypto.h crypto_aead_blocksize
1713-
!Finclude/linux/crypto.h crypto_aead_setkey
1714-
!Finclude/linux/crypto.h crypto_aead_setauthsize
1715-
!Finclude/linux/crypto.h crypto_aead_encrypt
1716-
!Finclude/linux/crypto.h crypto_aead_decrypt
1717+
!Pinclude/crypto/aead.h Authenticated Encryption With Associated Data (AEAD) Cipher API
1718+
!Finclude/crypto/aead.h crypto_alloc_aead
1719+
!Finclude/crypto/aead.h crypto_free_aead
1720+
!Finclude/crypto/aead.h crypto_aead_ivsize
1721+
!Finclude/crypto/aead.h crypto_aead_authsize
1722+
!Finclude/crypto/aead.h crypto_aead_blocksize
1723+
!Finclude/crypto/aead.h crypto_aead_setkey
1724+
!Finclude/crypto/aead.h crypto_aead_setauthsize
1725+
!Finclude/crypto/aead.h crypto_aead_encrypt
1726+
!Finclude/crypto/aead.h crypto_aead_decrypt
17171727
</sect1>
17181728
<sect1><title>Asynchronous AEAD Request Handle</title>
1719-
!Pinclude/linux/crypto.h Asynchronous AEAD Request Handle
1720-
!Finclude/linux/crypto.h crypto_aead_reqsize
1721-
!Finclude/linux/crypto.h aead_request_set_tfm
1722-
!Finclude/linux/crypto.h aead_request_alloc
1723-
!Finclude/linux/crypto.h aead_request_free
1724-
!Finclude/linux/crypto.h aead_request_set_callback
1725-
!Finclude/linux/crypto.h aead_request_set_crypt
1726-
!Finclude/linux/crypto.h aead_request_set_assoc
1729+
!Pinclude/crypto/aead.h Asynchronous AEAD Request Handle
1730+
!Finclude/crypto/aead.h crypto_aead_reqsize
1731+
!Finclude/crypto/aead.h aead_request_set_tfm
1732+
!Finclude/crypto/aead.h aead_request_alloc
1733+
!Finclude/crypto/aead.h aead_request_free
1734+
!Finclude/crypto/aead.h aead_request_set_callback
1735+
!Finclude/crypto/aead.h aead_request_set_crypt
1736+
!Finclude/crypto/aead.h aead_request_set_assoc
1737+
!Finclude/crypto/aead.h aead_request_set_ad
17271738
</sect1>
17281739
<sect1><title>Synchronous Block Cipher API</title>
17291740
!Pinclude/linux/crypto.h Synchronous Block Cipher API

‎Documentation/devicetree/bindings/crypto/fsl-sec2.txt

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
1-
Freescale SoC SEC Security Engines versions 2.x-3.x
1+
Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
22

33
Required properties:
44

55
- compatible : Should contain entries for this and backward compatible
6-
SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
6+
SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
7+
e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
8+
warning: SEC1 and SEC2 are mutually exclusive
79
- reg : Offset and length of the register set for the device
810
- interrupts : the SEC's interrupt number
911
- fsl,num-channels : An integer representing the number of channels

‎Documentation/devicetree/bindings/crypto/marvell-cesa.txt

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
Marvell Cryptographic Engines And Security Accelerator
2+
3+
Required properties:
4+
- compatible: should be one of the following string
5+
"marvell,orion-crypto"
6+
"marvell,kirkwood-crypto"
7+
"marvell,dove-crypto"
8+
"marvell,armada-370-crypto"
9+
"marvell,armada-xp-crypto"
10+
"marvell,armada-375-crypto"
11+
"marvell,armada-38x-crypto"
12+
- reg: base physical address of the engine and length of memory mapped
13+
region. Can also contain an entry for the SRAM attached to the CESA,
14+
but this representation is deprecated and marvell,crypto-srams should
15+
be used instead
16+
- reg-names: "regs". Can contain an "sram" entry, but this representation
17+
is deprecated and marvell,crypto-srams should be used instead
18+
- interrupts: interrupt number
19+
- clocks: reference to the crypto engines clocks. This property is not
20+
required for orion and kirkwood platforms
21+
- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine
22+
id.
23+
This property is not required for the orion and kirkwoord
24+
platforms.
25+
"cesazX" clocks are not required on armada-370 platforms
26+
- marvell,crypto-srams: phandle to crypto SRAM definitions
27+
28+
Optional properties:
29+
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30+
specified the whole SRAM is used (2KB)
31+
32+
33+
Examples:
34+
35+
crypto@90000 {
36+
compatible = "marvell,armada-xp-crypto";
37+
reg = <0x90000 0x10000>;
38+
reg-names = "regs";
39+
interrupts = <48>, <49>;
40+
clocks = <&gateclk 23>, <&gateclk 23>;
41+
clock-names = "cesa0", "cesa1";
42+
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
43+
marvell,crypto-sram-size = <0x600>;
44+
status = "okay";
45+
};

‎Documentation/devicetree/bindings/crypto/mv_cesa.txt

Lines changed: 22 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,33 @@
11
Marvell Cryptographic Engines And Security Accelerator
22

33
Required properties:
4-
- compatible : should be "marvell,orion-crypto"
5-
- reg : base physical address of the engine and length of memory mapped
6-
region, followed by base physical address of sram and its memory
7-
length
8-
- reg-names : "regs" , "sram";
9-
- interrupts : interrupt number
4+
- compatible: should be one of the following string
5+
"marvell,orion-crypto"
6+
"marvell,kirkwood-crypto"
7+
"marvell,dove-crypto"
8+
- reg: base physical address of the engine and length of memory mapped
9+
region. Can also contain an entry for the SRAM attached to the CESA,
10+
but this representation is deprecated and marvell,crypto-srams should
11+
be used instead
12+
- reg-names: "regs". Can contain an "sram" entry, but this representation
13+
is deprecated and marvell,crypto-srams should be used instead
14+
- interrupts: interrupt number
15+
- clocks: reference to the crypto engines clocks. This property is only
16+
required for Dove platforms
17+
- marvell,crypto-srams: phandle to crypto SRAM definitions
18+
19+
Optional properties:
20+
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21+
specified the whole SRAM is used (2KB)
1022

1123
Examples:
1224

1325
crypto@30000 {
1426
compatible = "marvell,orion-crypto";
15-
reg = <0x30000 0x10000>,
16-
<0x4000000 0x800>;
17-
reg-names = "regs" , "sram";
27+
reg = <0x30000 0x10000>;
28+
reg-names = "regs";
1829
interrupts = <22>;
30+
marvell,crypto-srams = <&crypto_sram>;
31+
marvell,crypto-sram-size = <0x600>;
1932
status = "okay";
2033
};

‎MAINTAINERS

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4879,13 +4879,23 @@ M: Marcelo Henrique Cerri <mhcerri@linux.vnet.ibm.com>
48794879
M: Fionnuala Gunter <fin@linux.vnet.ibm.com>
48804880
L: linux-crypto@vger.kernel.org
48814881
S: Supported
4882-
F: drivers/crypto/nx/
4882+
F: drivers/crypto/nx/Makefile
4883+
F: drivers/crypto/nx/Kconfig
4884+
F: drivers/crypto/nx/nx-aes*
4885+
F: drivers/crypto/nx/nx-sha*
4886+
F: drivers/crypto/nx/nx.*
4887+
F: drivers/crypto/nx/nx_csbcpb.h
4888+
F: drivers/crypto/nx/nx_debugfs.h
48834889

48844890
IBM Power 842 compression accelerator
48854891
M: Dan Streetman <ddstreet@us.ibm.com>
48864892
S: Supported
4887-
F: drivers/crypto/nx/nx-842.c
4888-
F: include/linux/nx842.h
4893+
F: drivers/crypto/nx/Makefile
4894+
F: drivers/crypto/nx/Kconfig
4895+
F: drivers/crypto/nx/nx-842*
4896+
F: include/linux/sw842.h
4897+
F: crypto/842.c
4898+
F: lib/842/
48894899

48904900
IBM Power Linux RAID adapter
48914901
M: Brian King <brking@us.ibm.com>

‎arch/arm/crypto/Kconfig

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -53,20 +53,13 @@ config CRYPTO_SHA256_ARM
5353
SHA-256 secure hash standard (DFIPS 180-2) implemented
5454
using optimized ARM assembler and NEON, when available.
5555

56-
config CRYPTO_SHA512_ARM_NEON
57-
tristate "SHA384 and SHA512 digest algorithm (ARM NEON)"
58-
depends on KERNEL_MODE_NEON
59-
select CRYPTO_SHA512
56+
config CRYPTO_SHA512_ARM
57+
tristate "SHA-384/512 digest algorithm (ARM-asm and NEON)"
6058
select CRYPTO_HASH
59+
depends on !CPU_V7M
6160
help
6261
SHA-512 secure hash standard (DFIPS 180-2) implemented
63-
using ARM NEON instructions, when available.
64-
65-
This version of SHA implements a 512 bit hash with 256 bits of
66-
security against collision attacks.
67-
68-
This code also includes SHA-384, a 384 bit hash with 192 bits
69-
of security against collision attacks.
62+
using optimized ARM assembler and NEON, when available.
7063

7164
config CRYPTO_AES_ARM
7265
tristate "AES cipher algorithms (ARM-asm)"

‎arch/arm/crypto/Makefile

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ obj-$(CONFIG_CRYPTO_AES_ARM_BS) += aes-arm-bs.o
77
obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
88
obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
99
obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
10-
obj-$(CONFIG_CRYPTO_SHA512_ARM_NEON) += sha512-arm-neon.o
10+
obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
1111

1212
ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
1313
ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
@@ -30,7 +30,8 @@ sha1-arm-y := sha1-armv4-large.o sha1_glue.o
3030
sha1-arm-neon-y := sha1-armv7-neon.o sha1_neon_glue.o
3131
sha256-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha256_neon_glue.o
3232
sha256-arm-y := sha256-core.o sha256_glue.o $(sha256-arm-neon-y)
33-
sha512-arm-neon-y := sha512-armv7-neon.o sha512_neon_glue.o
33+
sha512-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha512-neon-glue.o
34+
sha512-arm-y := sha512-core.o sha512-glue.o $(sha512-arm-neon-y)
3435
sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o
3536
sha2-arm-ce-y := sha2-ce-core.o sha2-ce-glue.o
3637
aes-arm-ce-y := aes-ce-core.o aes-ce-glue.o
@@ -45,4 +46,7 @@ $(src)/aesbs-core.S_shipped: $(src)/bsaes-armv7.pl
4546
$(src)/sha256-core.S_shipped: $(src)/sha256-armv4.pl
4647
$(call cmd,perl)
4748

48-
.PRECIOUS: $(obj)/aesbs-core.S $(obj)/sha256-core.S
49+
$(src)/sha512-core.S_shipped: $(src)/sha512-armv4.pl
50+
$(call cmd,perl)
51+
52+
.PRECIOUS: $(obj)/aesbs-core.S $(obj)/sha256-core.S $(obj)/sha512-core.S

‎arch/arm/crypto/aes-ce-core.S

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -101,15 +101,14 @@
101101
\dround q10, q11
102102
blo 0f @ AES-128: 10 rounds
103103
vld1.8 {q10-q11}, [ip]!
104-
beq 1f @ AES-192: 12 rounds
105104
\dround q12, q13
105+
beq 1f @ AES-192: 12 rounds
106106
vld1.8 {q12-q13}, [ip]
107107
\dround q10, q11
108108
0: \fround q12, q13, q14
109109
bx lr
110110

111-
1: \dround q12, q13
112-
\fround q10, q11, q14
111+
1: \fround q10, q11, q14
113112
bx lr
114113
.endm
115114

@@ -122,8 +121,8 @@
122121
* q2 : third in/output block (_3x version only)
123122
* q8 : first round key
124123
* q9 : secound round key
125-
* ip : address of 3rd round key
126124
* q14 : final round key
125+
* r2 : address of round key array
127126
* r3 : number of rounds
128127
*/
129128
.align 6

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