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Russell KingRussell King
Russell King
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Russell King
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[ARM] cachetype: move definitions to separate header
Rather than pollute asm/cacheflush.h with the cache type definitions, move them to asm/cachetype.h, and include this new header where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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7 files changed

+101
-90
lines changed

7 files changed

+101
-90
lines changed

‎arch/arm/include/asm/cacheflush.h

Lines changed: 0 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -444,94 +444,4 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
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dmac_inv_range(start, start + size);
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}
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#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
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#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
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#define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25))
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#define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25))
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#define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
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#define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
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#define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
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#define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
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#define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
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#define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
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#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIVT caches only
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*/
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#define cache_is_vivt() 1
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#define cache_is_vipt() 0
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#define cache_is_vipt_nonaliasing() 0
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#define cache_is_vipt_aliasing() 0
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#define icache_is_vivt_asid_tagged() 0
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIPT caches only
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*/
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#define cache_is_vivt() 0
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#define cache_is_vipt() 1
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#else
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/*
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* VIVT or VIPT caches. Note that this is unreliable since ARM926
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* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
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* There's no way to tell from the CacheType register what type (!)
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* the cache is.
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*/
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#define cache_is_vivt() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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(!__cacheid_present(__val)) || __cacheid_vivt(__val); \
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})
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#define cache_is_vipt() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_present(__val) && __cacheid_vipt(__val); \
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})
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_present(__val) && \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_present(__val) && \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
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__cacheid_present(__val) && \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#endif
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#endif

‎arch/arm/include/asm/cachetype.h

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
1+
#ifndef __ASM_ARM_CACHETYPE_H
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#define __ASM_ARM_CACHETYPE_H
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#include <asm/cputype.h>
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#define __cacheid_present(val) (val != read_cpuid_id())
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#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
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#define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25))
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#define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25))
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#define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
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#define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
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#define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
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#define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
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#define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
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#define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
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#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIVT caches only
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*/
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#define cache_is_vivt() 1
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#define cache_is_vipt() 0
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#define cache_is_vipt_nonaliasing() 0
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#define cache_is_vipt_aliasing() 0
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#define icache_is_vivt_asid_tagged() 0
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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/*
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* VIPT caches only
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*/
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#define cache_is_vivt() 0
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#define cache_is_vipt() 1
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#else
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/*
56+
* VIVT or VIPT caches. Note that this is unreliable since ARM926
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* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
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* There's no way to tell from the CacheType register what type (!)
59+
* the cache is.
60+
*/
61+
#define cache_is_vivt() \
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({ \
63+
unsigned int __val = read_cpuid_cachetype(); \
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(!__cacheid_present(__val)) || __cacheid_vivt(__val); \
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})
66+
67+
#define cache_is_vipt() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && __cacheid_vipt(__val); \
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})
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#define cache_is_vipt_nonaliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && \
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__cacheid_vipt_nonaliasing(__val); \
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})
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#define cache_is_vipt_aliasing() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
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__cacheid_present(__val) && \
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__cacheid_vipt_aliasing(__val); \
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})
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#define icache_is_vivt_asid_tagged() \
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({ \
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unsigned int __val = read_cpuid_cachetype(); \
90+
__cacheid_present(__val) && \
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__cacheid_vivt_asid_tagged_instr(__val); \
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})
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#endif
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#endif

‎arch/arm/include/asm/mmu_context.h

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@@ -15,6 +15,7 @@
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#include <linux/compiler.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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‎arch/arm/kernel/setup.c

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@@ -32,6 +32,7 @@
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/tlbflush.h>
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#include <asm/mach/arch.h>

‎arch/arm/mm/copypage-v6.c

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@@ -16,6 +16,7 @@
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#include <asm/shmparam.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include "mm.h"
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‎arch/arm/mm/fault-armv.c

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@@ -18,6 +18,7 @@
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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‎arch/arm/mm/flush.c

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@@ -12,6 +12,7 @@
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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