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634 | 634 | resets = <&cpg 219>;
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635 | 635 | #dma-cells = <1>;
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636 | 636 | dma-channels = <16>;
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| 637 | + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| 638 | + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, |
| 639 | + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, |
| 640 | + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, |
| 641 | + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, |
| 642 | + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, |
| 643 | + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, |
| 644 | + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; |
637 | 645 | };
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638 | 646 |
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639 | 647 | dmac1: dma-controller@e7300000 {
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668 | 676 | resets = <&cpg 218>;
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669 | 677 | #dma-cells = <1>;
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670 | 678 | dma-channels = <16>;
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| 679 | + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| 680 | + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, |
| 681 | + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, |
| 682 | + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, |
| 683 | + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, |
| 684 | + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, |
| 685 | + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, |
| 686 | + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; |
671 | 687 | };
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672 | 688 |
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673 | 689 | dmac2: dma-controller@e7310000 {
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702 | 718 | resets = <&cpg 217>;
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703 | 719 | #dma-cells = <1>;
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704 | 720 | dma-channels = <16>;
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| 721 | + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| 722 | + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, |
| 723 | + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, |
| 724 | + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, |
| 725 | + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, |
| 726 | + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, |
| 727 | + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, |
| 728 | + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; |
705 | 729 | };
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706 | 730 |
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707 | 731 | ipmmu_ds0: mmu@e6740000 {
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